Intel 253668-032US Benutzerhandbuch
Vol. 3 6-11
INTERRUPT AND EXCEPTION HANDLING
6.8.3
Masking Exceptions and Interrupts When Switching Stacks
To switch to a different stack segment, software often uses a pair of instructions, for
example:
example:
MOV SS, AX
MOV ESP, StackTop
MOV ESP, StackTop
If an interrupt or exception occurs after the segment selector has been loaded into
the SS register but before the ESP register has been loaded, these two parts of the
logical address into the stack space are inconsistent for the duration of the interrupt
or exception handler.
To prevent this situation, the processor inhibits interrupts, debug exceptions, and
single-step trap exceptions after either a MOV to SS instruction or a POP to SS
instruction, until the instruction boundary following the next instruction is reached.
All other faults may still be generated. If the LSS instruction is used to modify the
contents of the SS register (which is the recommended method of modifying this
register), this problem does not occur.
the SS register but before the ESP register has been loaded, these two parts of the
logical address into the stack space are inconsistent for the duration of the interrupt
or exception handler.
To prevent this situation, the processor inhibits interrupts, debug exceptions, and
single-step trap exceptions after either a MOV to SS instruction or a POP to SS
instruction, until the instruction boundary following the next instruction is reached.
All other faults may still be generated. If the LSS instruction is used to modify the
contents of the SS register (which is the recommended method of modifying this
register), this problem does not occur.
6.9
PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND
INTERRUPTS
If more than one exception or interrupt is pending at an instruction boundary, the
processor services them in a predictable order. Table 6-2 shows the priority among
classes of exception and interrupt sources.
processor services them in a predictable order. Table 6-2 shows the priority among
classes of exception and interrupt sources.
Table 6-2. Priority Among Simultaneous Exceptions and Interrupts
Priority
Description
1 (Highest)
Hardware Reset and Machine Checks
- RESET
- Machine Check
- RESET
- Machine Check
2
Trap on Task Switch
- T flag in TSS is set
- T flag in TSS is set
3
External Hardware Interventions
- FLUSH
- STOPCLK
- SMI
- INIT
- FLUSH
- STOPCLK
- SMI
- INIT
4
Traps on the Previous Instruction
- Breakpoints
- Debug Trap Exceptions (TF flag set or data/I-O breakpoint)
- Breakpoints
- Debug Trap Exceptions (TF flag set or data/I-O breakpoint)