Intel 253668-032US Benutzerhandbuch
Vol. 3 8-37
MULTIPLE-PROCESSOR MANAGEMENT
During initialization, each logical processor is assigned an APIC ID that is stored in
the local APIC ID register for each logical processor. If two or more processors
supporting Intel Hyper-Threading Technology are present, each logical processor on
the system bus is assigned a unique ID (see Section 8.9.3, “Hierarchical ID of Logical
Processors in an MP System”). Once logical processors have APIC IDs, software
communicates with them by sending APIC IPI messages.
the local APIC ID register for each logical processor. If two or more processors
supporting Intel Hyper-Threading Technology are present, each logical processor on
the system bus is assigned a unique ID (see Section 8.9.3, “Hierarchical ID of Logical
Processors in an MP System”). Once logical processors have APIC IDs, software
communicates with them by sending APIC IPI messages.
8.6.2
Initializing Multi-Core Processors
The initialization process for an MP system that contains multi-core Intel 64 or IA-32
processors is the same as for conventional MP systems (see Section 8.4, “Multiple-
Processor (MP) Initialization”). A logical processor in one core is selected as the BSP;
other logical processors are designated as APs.
During initialization, each logical processor is assigned an APIC ID. Once logical
processors have APIC IDs, software may communicate with them by sending APIC
IPI messages.
processors is the same as for conventional MP systems (see Section 8.4, “Multiple-
Processor (MP) Initialization”). A logical processor in one core is selected as the BSP;
other logical processors are designated as APs.
During initialization, each logical processor is assigned an APIC ID. Once logical
processors have APIC IDs, software may communicate with them by sending APIC
IPI messages.
8.6.3
Executing Multiple Threads on an Intel
®
64 or IA-32
Processor Supporting Hardware Multi-Threading
Upon completing the operating system boot-up procedure, the bootstrap processor
(BSP) executes operating system code. Other logical processors are placed in the
halt state. To execute a code stream (thread) on a halted logical processor, the oper-
ating system issues an interprocessor interrupt (IPI) addressed to the halted logical
processor. In response to the IPI, the processor wakes up and begins executing the
thread identified by the interrupt vector received as part of the IPI.
To manage execution of multiple threads on logical processors, an operating system
can use conventional symmetric multiprocessing (SMP) techniques. For example, the
operating-system can use a time-slice or load balancing mechanism to periodically
interrupt each of the active logical processors. Upon interrupting a logical processor,
the operating system checks its run queue for a thread waiting to be executed and
dispatches the thread to the interrupted logical processor.
(BSP) executes operating system code. Other logical processors are placed in the
halt state. To execute a code stream (thread) on a halted logical processor, the oper-
ating system issues an interprocessor interrupt (IPI) addressed to the halted logical
processor. In response to the IPI, the processor wakes up and begins executing the
thread identified by the interrupt vector received as part of the IPI.
To manage execution of multiple threads on logical processors, an operating system
can use conventional symmetric multiprocessing (SMP) techniques. For example, the
operating-system can use a time-slice or load balancing mechanism to periodically
interrupt each of the active logical processors. Upon interrupting a logical processor,
the operating system checks its run queue for a thread waiting to be executed and
dispatches the thread to the interrupted logical processor.
8.6.4
Handling Interrupts on an IA-32 Processor Supporting
Hardware Multi-Threading
Interrupts are handled on processors supporting Intel Hyper-Threading Technology
as they are on conventional MP systems. External interrupts are received by the I/O
APIC, which distributes them as interrupt messages to specific logical processors
(see Figure 8-3).
Logical processors can also send IPIs to other logical processors by writing to the ICR
register of its local APIC (see Section 10.7, “Issuing Interprocessor Interrupts”). This
also applies to dual-core processors.
as they are on conventional MP systems. External interrupts are received by the I/O
APIC, which distributes them as interrupt messages to specific logical processors
(see Figure 8-3).
Logical processors can also send IPIs to other logical processors by writing to the ICR
register of its local APIC (see Section 10.7, “Issuing Interprocessor Interrupts”). This
also applies to dual-core processors.