Intel 253668-032US Benutzerhandbuch
Vol. 3 8-39
MULTIPLE-PROCESSOR MANAGEMENT
8.7.1
State of the Logical Processors
The following features are part of the architectural state of logical processors within
Intel 64 or IA-32 processors supporting Intel Hyper-Threading Technology. The
features can be subdivided into three groups:
Intel 64 or IA-32 processors supporting Intel Hyper-Threading Technology. The
features can be subdivided into three groups:
•
Duplicated for each logical processor
•
Shared by logical processors in a physical processor
•
Shared or duplicated, depending on the implementation
The following features are duplicated for each logical processor:
•
General purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, and EBP)
•
Segment registers (CS, DS, SS, ES, FS, and GS)
•
EFLAGS and EIP registers. Note that the CS and EIP/RIP registers for each logical
processor point to the instruction stream for the thread being executed by the
logical processor.
processor point to the instruction stream for the thread being executed by the
logical processor.
•
x87 FPU registers (ST0 through ST7, status word, control word, tag word, data
operand pointer, and instruction pointer)
operand pointer, and instruction pointer)
•
MMX registers (MM0 through MM7)
•
XMM registers (XMM0 through XMM7) and the MXCSR register
•
Control registers and system table pointer registers (GDTR, LDTR, IDTR, task
register)
register)
Figure 8-4. IA-32 Processor with Two Logical Processors Supporting Intel HT
Technology
Logical
Processor 0
Architectural
State
Bus Interface
Local APIC
Local APIC
Logical
Processor 1
Architectural
State
Execution Engine
System Bus