Intel 253668-032US Benutzerhandbuch
9-10 Vol. 3
PROCESSOR MANAGEMENT AND INITIALIZATION
all the MTRRs must be cleared to 0, which selects the uncached (UC) memory type.
See Section 11.11, “Memory Type Range Registers (MTRRs),” for detailed informa-
tion on the MTRRs.
See Section 11.11, “Memory Type Range Registers (MTRRs),” for detailed informa-
tion on the MTRRs.
9.6 INITIALIZING
SSE/SSE2/SSE3/SSSE3
EXTENSIONS
For processors that contain SSE/SSE2/SSE3/SSSE3 extensions, steps must be taken
when initializing the processor to allow execution of these instructions.
1. Check the CPUID feature flags for the presence of the SSE/SSE2/SSE3/SSSE3
when initializing the processor to allow execution of these instructions.
1. Check the CPUID feature flags for the presence of the SSE/SSE2/SSE3/SSSE3
extensions (respectively: EDX bits 25 and 26, ECX bit 0 and 9) and support for
the FXSAVE and FXRSTOR instructions (EDX bit 24). Also check for support for
the CLFLUSH instruction (EDX bit 19). The CPUID feature flags are loaded in the
EDX and ECX registers when the CPUID instruction is executed with a 1 in the
EAX register.
the FXSAVE and FXRSTOR instructions (EDX bit 24). Also check for support for
the CLFLUSH instruction (EDX bit 19). The CPUID feature flags are loaded in the
EDX and ECX registers when the CPUID instruction is executed with a 1 in the
EAX register.
2. Set the OSFXSR flag (bit 9 in control register CR4) to indicate that the operating
system supports saving and restoring the SSE/SSE2/SSE3/SSSE3 execution
environment (XXM and MXCSR registers) with the FXSAVE and FXRSTOR instruc-
tions, respectively. See Section 2.5, “Control Registers,” for a description of the
OSFXSR flag.
environment (XXM and MXCSR registers) with the FXSAVE and FXRSTOR instruc-
tions, respectively. See Section 2.5, “Control Registers,” for a description of the
OSFXSR flag.
3. Set the OSXMMEXCPT flag (bit 10 in control register CR4) to indicate that the
operating system supports the handling of SSE/SSE2/SSE3 SIMD floating-point
exceptions (#XF). See Section 2.5, “Control Registers,” for a description of the
OSXMMEXCPT flag.
exceptions (#XF). See Section 2.5, “Control Registers,” for a description of the
OSXMMEXCPT flag.
4. Set the mask bits and flags in the MXCSR register according to the mode of
operation desired for SSE/SSE2/SSE3 SIMD floating-point instructions. See
“MXCSR Control and Status Register” in Chapter 10, “Programming with
Streaming SIMD Extensions (SSE),” of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1, for a detailed description of the bits and
flags in the MXCSR register.
“MXCSR Control and Status Register” in Chapter 10, “Programming with
Streaming SIMD Extensions (SSE),” of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1, for a detailed description of the bits and
flags in the MXCSR register.
9.7
SOFTWARE INITIALIZATION FOR REAL-ADDRESS
MODE OPERATION
Following a hardware reset (either through a power-up or the assertion of the
RESET# pin) the processor is placed in real-address mode and begins executing soft-
ware initialization code from physical address FFFFFFF0H. Software initialization code
must first set up the necessary data structures for handling basic system functions,
such as a real-mode IDT for handling interrupts and exceptions. If the processor is to
remain in real-address mode, software must then load additional operating-system
or executive code modules and data structures to allow reliable execution of applica-
tion programs in real-address mode.
If the processor is going to operate in protected mode, software must load the neces-
sary data structures to operate in protected mode and then switch to protected
RESET# pin) the processor is placed in real-address mode and begins executing soft-
ware initialization code from physical address FFFFFFF0H. Software initialization code
must first set up the necessary data structures for handling basic system functions,
such as a real-mode IDT for handling interrupts and exceptions. If the processor is to
remain in real-address mode, software must then load additional operating-system
or executive code modules and data structures to allow reliable execution of applica-
tion programs in real-address mode.
If the processor is going to operate in protected mode, software must load the neces-
sary data structures to operate in protected mode and then switch to protected