Intel 253668-032US Benutzerhandbuch
Vol. 3 9-11
PROCESSOR MANAGEMENT AND INITIALIZATION
mode. The protected-mode data structures that must be loaded are described in
Section 9.8, “Software Initialization for Protected-Mode Operation.”
Section 9.8, “Software Initialization for Protected-Mode Operation.”
9.7.1
Real-Address Mode IDT
In real-address mode, the only system data structure that must be loaded into
memory is the IDT (also called the “interrupt vector table”). By default, the address
of the base of the IDT is physical address 0H. This address can be changed by using
the LIDT instruction to change the base address value in the IDTR. Software initial-
ization code needs to load interrupt- and exception-handler pointers into the IDT
before interrupts can be enabled.
The actual interrupt- and exception-handler code can be contained either in EPROM
or RAM; however, the code must be located within the 1-MByte addressable range of
the processor in real-address mode. If the handler code is to be stored in RAM, it
must be loaded along with the IDT.
memory is the IDT (also called the “interrupt vector table”). By default, the address
of the base of the IDT is physical address 0H. This address can be changed by using
the LIDT instruction to change the base address value in the IDTR. Software initial-
ization code needs to load interrupt- and exception-handler pointers into the IDT
before interrupts can be enabled.
The actual interrupt- and exception-handler code can be contained either in EPROM
or RAM; however, the code must be located within the 1-MByte addressable range of
the processor in real-address mode. If the handler code is to be stored in RAM, it
must be loaded along with the IDT.
9.7.2
NMI Interrupt Handling
The NMI interrupt is always enabled (except when multiple NMIs are nested). If the
IDT and the NMI interrupt handler need to be loaded into RAM, there will be a period
of time following hardware reset when an NMI interrupt cannot be handled. During
this time, hardware must provide a mechanism to prevent an NMI interrupt from
halting code execution until the IDT and the necessary NMI handler software is
loaded. Here are two examples of how NMIs can be handled during the initial states
of processor initialization:
IDT and the NMI interrupt handler need to be loaded into RAM, there will be a period
of time following hardware reset when an NMI interrupt cannot be handled. During
this time, hardware must provide a mechanism to prevent an NMI interrupt from
halting code execution until the IDT and the necessary NMI handler software is
loaded. Here are two examples of how NMIs can be handled during the initial states
of processor initialization:
•
A simple IDT and NMI interrupt handler can be provided in EPROM. This allows an
NMI interrupt to be handled immediately after reset initialization.
NMI interrupt to be handled immediately after reset initialization.
•
The system hardware can provide a mechanism to enable and disable NMIs by
passing the NMI# signal through an AND gate controlled by a flag in an I/O port.
Hardware can clear the flag when the processor is reset, and software can set the
flag when it is ready to handle NMI interrupts.
passing the NMI# signal through an AND gate controlled by a flag in an I/O port.
Hardware can clear the flag when the processor is reset, and software can set the
flag when it is ready to handle NMI interrupts.
9.8
SOFTWARE INITIALIZATION FOR PROTECTED-MODE
OPERATION
The processor is placed in real-address mode following a hardware reset. At this
point in the initialization process, some basic data structures and code modules must
be loaded into physical memory to support further initialization of the processor, as
described in Section 9.7, “Software Initialization for Real-Address Mode Operation.”
Before the processor can be switched to protected mode, the software initialization
code must load a minimum number of protected mode data structures and code
point in the initialization process, some basic data structures and code modules must
be loaded into physical memory to support further initialization of the processor, as
described in Section 9.7, “Software Initialization for Real-Address Mode Operation.”
Before the processor can be switched to protected mode, the software initialization
code must load a minimum number of protected mode data structures and code