Intel 253668-032US Benutzerhandbuch
Vol. 3 9-13
PROCESSOR MANAGEMENT AND INITIALIZATION
descriptors in the GDT. Some operating systems allocate new segments and LDTs as
they are needed. This provides maximum flexibility for handling a dynamic program-
ming environment. However, many operating systems use a single LDT for all tasks,
allocating GDT entries in advance. An embedded system, such as a process
controller, might pre-allocate a fixed number of segments and LDTs for a fixed
number of application programs. This would be a simple and efficient way to struc-
ture the software environment of a real-time system.
they are needed. This provides maximum flexibility for handling a dynamic program-
ming environment. However, many operating systems use a single LDT for all tasks,
allocating GDT entries in advance. An embedded system, such as a process
controller, might pre-allocate a fixed number of segments and LDTs for a fixed
number of application programs. This would be a simple and efficient way to struc-
ture the software environment of a real-time system.
9.8.2
Initializing Protected-Mode Exceptions and Interrupts
Software initialization code must at a minimum load a protected-mode IDT with gate
descriptor for each exception vector that the processor can generate. If interrupt or
trap gates are used, the gate descriptors can all point to the same code segment,
which contains the necessary exception handlers. If task gates are used, one TSS
and accompanying code, data, and task segments are required for each exception
handler called with a task gate.
If hardware allows interrupts to be generated, gate descriptors must be provided in
the IDT for one or more interrupt handlers.
Before the IDT can be used, the base address and limit for the IDT must be loaded
into the IDTR register using an LIDT instruction. This operation is typically carried out
immediately after switching to protected mode.
descriptor for each exception vector that the processor can generate. If interrupt or
trap gates are used, the gate descriptors can all point to the same code segment,
which contains the necessary exception handlers. If task gates are used, one TSS
and accompanying code, data, and task segments are required for each exception
handler called with a task gate.
If hardware allows interrupts to be generated, gate descriptors must be provided in
the IDT for one or more interrupt handlers.
Before the IDT can be used, the base address and limit for the IDT must be loaded
into the IDTR register using an LIDT instruction. This operation is typically carried out
immediately after switching to protected mode.
9.8.3 Initializing
Paging
Paging is controlled by the PG flag in control register CR0. When this flag is clear (its
state following a hardware reset), the paging mechanism is turned off; when it is set,
paging is enabled. Before setting the PG flag, the following data structures and regis-
ters must be initialized:
state following a hardware reset), the paging mechanism is turned off; when it is set,
paging is enabled. Before setting the PG flag, the following data structures and regis-
ters must be initialized:
•
Software must load at least one page directory and one page table into physical
memory. The page table can be eliminated if the page directory contains a
directory entry pointing to itself (here, the page directory and page table reside
in the same page), or if only 4-MByte pages are used.
memory. The page table can be eliminated if the page directory contains a
directory entry pointing to itself (here, the page directory and page table reside
in the same page), or if only 4-MByte pages are used.
•
Control register CR3 (also called the PDBR register) is loaded with the physical
base address of the page directory.
base address of the page directory.
•
(Optional) Software may provide one set of code and data descriptors in the GDT
or in an LDT for supervisor mode and another set for user mode.
or in an LDT for supervisor mode and another set for user mode.
With this paging initialization complete, paging is enabled and the processor is
switched to protected mode at the same time by loading control register CR0 with an
image in which the PG and PE flags are set. (Paging cannot be enabled before the
processor is switched to protected mode.)
switched to protected mode at the same time by loading control register CR0 with an
image in which the PG and PE flags are set. (Paging cannot be enabled before the
processor is switched to protected mode.)