Intel 253668-032US Benutzerhandbuch
10-30 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.6
HANDLING LOCAL INTERRUPTS
The following sections describe facilities that are provided in the local APIC for
handling local interrupts. These include: the processor’s LINT0 and LINT1 pins, the
APIC timer, the performance-monitoring counters, the thermal sensor, and the
internal APIC error detector. Local interrupt handling facilities include: the LVT, the
error status register (ESR), the divide configuration register (DCR), and the initial
count and current count registers.
handling local interrupts. These include: the processor’s LINT0 and LINT1 pins, the
APIC timer, the performance-monitoring counters, the thermal sensor, and the
internal APIC error detector. Local interrupt handling facilities include: the LVT, the
error status register (ESR), the divide configuration register (DCR), and the initial
count and current count registers.
10.6.1
Local Vector Table
The local vector table (LVT) allows software to specify the manner in which the local
interrupts are delivered to the processor core. It consists of the following 32-bit APIC
registers (see
interrupts are delivered to the processor core. It consists of the following 32-bit APIC
registers (see
), one for each local interrupt:
•
LVT Timer Register (FEE0 0320H) — Specifies interrupt delivery when the
APIC timer signals an interrupt (see
APIC timer signals an interrupt (see
).
•
LVT Thermal Monitor Register (FEE0 0330H) — Specifies interrupt delivery
when the thermal sensor generates an interrupt (see Section 14.5.2, “Thermal
Monitor”). This LVT entry is implementation specific, not architectural. If imple-
mented, it will always be at base address FEE0 0330H.
when the thermal sensor generates an interrupt (see Section 14.5.2, “Thermal
Monitor”). This LVT entry is implementation specific, not architectural. If imple-
mented, it will always be at base address FEE0 0330H.
•
LVT Performance Counter Register (FEE0 0340H) — Specifies interrupt
delivery when a performance counter generates an interrupt on overflow (see
Section 30.8.5.8, “Generating an Interrupt on Overflow”). This LVT entry is
implementation specific, not architectural. If implemented, it is not guaranteed
to be at base address FEE0 0340H.
delivery when a performance counter generates an interrupt on overflow (see
Section 30.8.5.8, “Generating an Interrupt on Overflow”). This LVT entry is
implementation specific, not architectural. If implemented, it is not guaranteed
to be at base address FEE0 0340H.
•
LVT LINT0 Register (FEE0 0350H) — Specifies interrupt delivery when an
interrupt is signaled at the LINT0 pin.
interrupt is signaled at the LINT0 pin.
•
LVT LINT1 Register (FEE0 0360H) — Specifies interrupt delivery when an
interrupt is signaled at the LINT1 pin.
interrupt is signaled at the LINT1 pin.
•
LVT Error Register (FEE0 0370H) — Specifies interrupt delivery when the
APIC detects an internal error (see
APIC detects an internal error (see
•
CMCI LVT Register (FEE0 02F0H) — Specifies interrupt delivery when an
overflow condition of corrected machine check error count reaching a threshold
value occurred in a machine check bank supporting CMCI (see
overflow condition of corrected machine check error count reaching a threshold
value occurred in a machine check bank supporting CMCI (see
).
The LVT performance counter register and its associated interrupt were introduced in
the P6 processors and are also present in the Pentium 4 and Intel Xeon processors.
The LVT thermal monitor register and its associated interrupt were introduced in the
Pentium 4 and Intel Xeon processors.
As shown in
the P6 processors and are also present in the Pentium 4 and Intel Xeon processors.
The LVT thermal monitor register and its associated interrupt were introduced in the
Pentium 4 and Intel Xeon processors.
As shown in
, some of these fields and flags are not available (and
reserved) for some entries.