Intel 253668-032US Benutzerhandbuch
Vol. 3 10-29
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The extended topology enumeration leaf is intended to assist software with enumer-
ating processor topology on systems that requires 32-bit x2APIC IDs to address indi-
vidual logical processors. For example, a system with greater than 256 logical
processors or greater than 64 processor cores will require the OS to use 32-bit
x2APIC IDs. Details of CPUID leaf 0BH can be found in the reference pages of CPUID
in Chapter 3 of Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
Processor topology enumeration algorithm for processors supporting the extended
topology enumeration leaf of CPUID and processors that do not support CPUID leaf
0BH are treated in Section 8.9.4, “Algorithm for Three-Level Mappings of APIC_ID”.
ating processor topology on systems that requires 32-bit x2APIC IDs to address indi-
vidual logical processors. For example, a system with greater than 256 logical
processors or greater than 64 processor cores will require the OS to use 32-bit
x2APIC IDs. Details of CPUID leaf 0BH can be found in the reference pages of CPUID
in Chapter 3 of Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
Processor topology enumeration algorithm for processors supporting the extended
topology enumeration leaf of CPUID and processors that do not support CPUID leaf
0BH are treated in Section 8.9.4, “Algorithm for Three-Level Mappings of APIC_ID”.
10.5.8.1 Consistency of APIC IDs and CPUID
The consistency of physical x2APIC ID in MSR 802H in x2APIC mode and the 32-bit
value returned in CPUID.0BH:EDX is facilitated by processor hardware.
CPUID.0BH:EDX will report the full 32 bit ID, in xAPIC and x2APIC mode. This allows
BIOS to determine if a system has processors with IDs exceeding the 8-bit initial
APIC ID limit (CPUID.01H:EBX[31:24]). Initial APIC ID (CPUID.01H:EBX[31:24]) is
always equal to CPUID.0BH:EDX[7:0].
If the values of CPUID.0BH:EDX reported by all logical processors in a system are
less than 255, BIOS can transfer control to OS in xAPIC mode.
If the values of CPUID.0BH:EDX reported by some logical processors in a system are
greater or equal than 255, BIOS must support two options to hand off to OS:
value returned in CPUID.0BH:EDX is facilitated by processor hardware.
CPUID.0BH:EDX will report the full 32 bit ID, in xAPIC and x2APIC mode. This allows
BIOS to determine if a system has processors with IDs exceeding the 8-bit initial
APIC ID limit (CPUID.01H:EBX[31:24]). Initial APIC ID (CPUID.01H:EBX[31:24]) is
always equal to CPUID.0BH:EDX[7:0].
If the values of CPUID.0BH:EDX reported by all logical processors in a system are
less than 255, BIOS can transfer control to OS in xAPIC mode.
If the values of CPUID.0BH:EDX reported by some logical processors in a system are
greater or equal than 255, BIOS must support two options to hand off to OS:
•
If BIOS enables logical processors with x2APIC IDs greater than 255, then it
should enable X2APIC in Boot Strap Processor (BSP) and all Application
Processors (AP) before passing control to the OS. Application requiring processor
topology information must use OS provided services based on x2APIC IDs or
CPUID.0BH leaf.
should enable X2APIC in Boot Strap Processor (BSP) and all Application
Processors (AP) before passing control to the OS. Application requiring processor
topology information must use OS provided services based on x2APIC IDs or
CPUID.0BH leaf.
•
If a BIOS transfers control to OS in xAPIC mode, then the BIOS must ensure that
only logical processors with CPUID.0BH.EDX value less than 255 are enabled.
BIOS initialization on all logical processors with CPUID.0B.EDX values greater
than or equal to 255 must (a) disable APIC and execute CLI in each logical
processor, and (b) leave these logical processor in the lowest power state so that
these processors do not respond to INIT IPI during OS boot. The BSP and all the
enabled logical processor operate in xAPIC mode after BIOS passed control to
OS. Application requiring processor topology information can use OS provided
legacy services based on 8-bit initial APIC IDs or legacy topology information
from CPUID.01H and CPUID 04H leaves. Even if the BIOS passes control in xAPIC
mode, an OS can switch the processors to x2APIC mode later. BIOS SMM handler
should always read the APIC_BASE_MSR, determine the APIC mode and use the
corresponding access method.
only logical processors with CPUID.0BH.EDX value less than 255 are enabled.
BIOS initialization on all logical processors with CPUID.0B.EDX values greater
than or equal to 255 must (a) disable APIC and execute CLI in each logical
processor, and (b) leave these logical processor in the lowest power state so that
these processors do not respond to INIT IPI during OS boot. The BSP and all the
enabled logical processor operate in xAPIC mode after BIOS passed control to
OS. Application requiring processor topology information can use OS provided
legacy services based on 8-bit initial APIC IDs or legacy topology information
from CPUID.01H and CPUID 04H leaves. Even if the BIOS passes control in xAPIC
mode, an OS can switch the processors to x2APIC mode later. BIOS SMM handler
should always read the APIC_BASE_MSR, determine the APIC mode and use the
corresponding access method.