Intel 253668-032US Benutzerhandbuch
10-62 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
•
Loading the TPR with a value of 8 (01000B) blocks all interrupts with a priority of
8 or less while allowing all interrupts with a priority of nine or more to be
recognized.
8 or less while allowing all interrupts with a priority of nine or more to be
recognized.
•
Loading the TPR with zero enables all external interrupts.
•
Loading the TPR with 0F (01111B) disables all external interrupts.
The TPR (shown in
) is cleared to 0 on reset. In 64-bit mode, software
can read and write the TPR using an alternate interface, MOV CR8 instruction. The
new priority level is established when the MOV CR8 instruction completes execution.
Software does not need to force serialization after loading the TPR using MOV CR8.
Use of the MOV CRn instruction requires a privilege level of 0. Programs running at
privilege level greater than 0 cannot read or write the TPR. An attempt to do so
results in a general-protection exception, #GP(0). The TPR is abstracted from the
interrupt controller (IC), which prioritizes and manages external interrupt delivery to
the processor. The IC can be an external device, such as an APIC or 8259. Typically,
the IC provides a priority mechanism similar or identical to the TPR. The IC, however,
is considered implementation-dependent with the under-lying priority mechanisms
subject to change. CR8, by contrast, is part of the Intel 64 architecture. Software can
depend on this definition remaining unchanged.
new priority level is established when the MOV CR8 instruction completes execution.
Software does not need to force serialization after loading the TPR using MOV CR8.
Use of the MOV CRn instruction requires a privilege level of 0. Programs running at
privilege level greater than 0 cannot read or write the TPR. An attempt to do so
results in a general-protection exception, #GP(0). The TPR is abstracted from the
interrupt controller (IC), which prioritizes and manages external interrupt delivery to
the processor. The IC can be an external device, such as an APIC or 8259. Typically,
the IC provides a priority mechanism similar or identical to the TPR. The IC, however,
is considered implementation-dependent with the under-lying priority mechanisms
subject to change. CR8, by contrast, is part of the Intel 64 architecture. Software can
depend on this definition remaining unchanged.
shows the layout of CR8; only the low four bits are used. The remaining
60 bits are reserved and must be written with zeros. Failure to do this results in a
general-protection exception, #GP(0).
general-protection exception, #GP(0).
10.9.6.1 Interaction of Task Priorities between CR8 and APIC
The first implementation of Intel 64 architecture includes a local advanced program-
mable interrupt controller (APIC) that is similar to the APIC used with previous IA-32
processors. Some aspects of the local APIC affect the operation of the architecturally
defined task priority register and the programming interface using CR8.
Notable CR8 and APIC interactions are:
mable interrupt controller (APIC) that is similar to the APIC used with previous IA-32
processors. Some aspects of the local APIC affect the operation of the architecturally
defined task priority register and the programming interface using CR8.
Notable CR8 and APIC interactions are:
•
The processor powers up with the local APIC enabled.
•
The APIC must be enabled for CR8 to function as the TPR. Writes to CR8 are
reflected into the APIC Task Priority Register.
reflected into the APIC Task Priority Register.
•
APIC.TPR[bits 7:4] = CR8[bits 3:0], APIC.TPR[bits 3:0] = 0. A read of CR8
returns a 64-bit value which is the value of TPR[bits 7:4], zero extended to 64
bits.
returns a 64-bit value which is the value of TPR[bits 7:4], zero extended to 64
bits.
Figure 10-30. CR8 Register
63
0
Value after reset: 0H
3
4
Reserved