Intel 253668-032US Benutzerhandbuch
Vol. 3 10-63
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
There are no ordering mechanisms between direct updates of the APIC.TPR and CR8.
Operating software should implement either direct APIC TPR updates or CR8 style
TPR updates but not mix them. Software can use a serializing instruction (for
example, CPUID) to serialize updates between MOV CR8 and stores to the APIC.
Operating software should implement either direct APIC TPR updates or CR8 style
TPR updates but not mix them. Software can use a serializing instruction (for
example, CPUID) to serialize updates between MOV CR8 and stores to the APIC.
10.10 SPURIOUS
INTERRUPT
A special situation may occur when a processor raises its task priority to be greater
than or equal to the level of the interrupt for which the processor INTR signal is
currently being asserted. If at the time the INTA cycle is issued, the interrupt that
was to be dispensed has become masked (programmed by software), the local APIC
will deliver a spurious-interrupt vector. Dispensing the spurious-interrupt vector does
not affect the ISR, so the handler for this vector should return without an EOI.
The vector number for the spurious-interrupt vector is specified in the spurious-inter-
rupt vector register (see
than or equal to the level of the interrupt for which the processor INTR signal is
currently being asserted. If at the time the INTA cycle is issued, the interrupt that
was to be dispensed has become masked (programmed by software), the local APIC
will deliver a spurious-interrupt vector. Dispensing the spurious-interrupt vector does
not affect the ISR, so the handler for this vector should return without an EOI.
The vector number for the spurious-interrupt vector is specified in the spurious-inter-
rupt vector register (see
). The functions of the fields in this register are
as follows:
Spurious Vector
Spurious Vector
Determines the vector number to be delivered to the processor
when the local APIC generates a spurious vector.
(Pentium 4 and Intel Xeon processors.) Bits 0 through 7 of the
this field are programmable by software.
(P6 family and Pentium processors). Bits 4 through 7 of the this
field are programmable by software, and bits 0 through 3 are
hardwired to logical ones. Software writes to bits 0 through 3
have no effect.
hardwired to logical ones. Software writes to bits 0 through 3
have no effect.
APIC Software
Allows software to temporarily enable (1) or disable (0) the local
Enable/Disable
APIC (see
Focus Processor Determines if focus processor checking is enabled (0) or
disabled (1)
Checking
when using the lowest-priority delivery mode. In Pentium 4 and
Intel Xeon processors, this bit is reserved and should be cleared
to 0.
to 0.
NOTE
Do not program an LVT or IOAPIC RTE with a spurious vector even if
you set the mask bit. A spurious vector ISR does not do an EOI. If for
some reason an interrupt is generated by an LVT or RTE entry, the bit
in the in-service register will be left set for the spurious vector. This
will mask all interrupts at the same or lower priority
you set the mask bit. A spurious vector ISR does not do an EOI. If for
some reason an interrupt is generated by an LVT or RTE entry, the bit
in the in-service register will be left set for the spurious vector. This
will mask all interrupts at the same or lower priority