Intel 253668-032US Benutzerhandbuch
13-2 Vol. 3
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR
guidelines for this support. Because SSE/SSE2/SSE3/SSSE3/SSE4 extensions share
the same state, experience the same sets of non-numerical and numerical exception
behavior, these guidelines that apply to SSE also apply to other sets of SIMD exten-
sions that operate on the same processor state and subject to the same sets of of
non-numerical and numerical exception behavior.
Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE2),” and Chapter
12, “Programming with SSE3, SSSE3 and SSE4,” in the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1, discuss support for
SSE/SSE2/SSE3/SSSE3/SSE4 from an applications point of view program.
the same state, experience the same sets of non-numerical and numerical exception
behavior, these guidelines that apply to SSE also apply to other sets of SIMD exten-
sions that operate on the same processor state and subject to the same sets of of
non-numerical and numerical exception behavior.
Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE2),” and Chapter
12, “Programming with SSE3, SSSE3 and SSE4,” in the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1, discuss support for
SSE/SSE2/SSE3/SSSE3/SSE4 from an applications point of view program.
13.1.1
Adding Support to an Operating System for
SSE/SSE2/SSE3/SSSE3/SSE4 Extensions
The following guidelines describe functions that an operating system or executive
must perform to support SSE/SSE2/SSE3/SSSE3/SSE4 extensions:
1. Check that the processor supports the SSE/SSE2/SSE3/SSSE3/SSE4 extensions.
2. Check that the processor supports the FXSAVE and FXRSTOR instructions.
3. Provide an initialization for the SSE, SSE2 SSE3, SSSE3 and SSE4 states.
4. Provide support for the FXSAVE and FXRSTOR instructions.
5. Provide support (if necessary) in non-numeric exception handlers for exceptions
must perform to support SSE/SSE2/SSE3/SSSE3/SSE4 extensions:
1. Check that the processor supports the SSE/SSE2/SSE3/SSSE3/SSE4 extensions.
2. Check that the processor supports the FXSAVE and FXRSTOR instructions.
3. Provide an initialization for the SSE, SSE2 SSE3, SSSE3 and SSE4 states.
4. Provide support for the FXSAVE and FXRSTOR instructions.
5. Provide support (if necessary) in non-numeric exception handlers for exceptions
generated by the SSE, SSE2, SSE3 and SSE4 instructions.
6. Provide an exception handler for the SIMD floating-point exception (#XM).
The following sections describe how to implement each of these guidelines.
The following sections describe how to implement each of these guidelines.
13.1.2
Checking for SSE/SSE2/SSE3/SSSE3/SSE4 Extension
Support
If the processor attempts to execute an unsupported SSE/SSE2/SSE3/SSSE3/SSE4
instruction, the processor generates an invalid-opcode exception (#UD).
Before an operating system or executive attempts to use
SSE/SSE2/SSE3/SSSE3/SSE4 extensions, it should check that support is present.
Make sure:
instruction, the processor generates an invalid-opcode exception (#UD).
Before an operating system or executive attempts to use
SSE/SSE2/SSE3/SSSE3/SSE4 extensions, it should check that support is present.
Make sure:
•
CPUID.1:EDX.SSE[bit 25] = 1
•
CPUID.1:EDX.SSE2[bit 26] = 1
•
CPUID.1:ECX.SSE3[bit 0] = 1
•
CPUID.1:ECX.SSSE3[bit 9] = 1
•
CPUID.1:ECX.SSE4_1[bit 19] = 1
•
CPUID.1:ECX.SSE4_2[bit 20] = 1