Intel 253668-032US Benutzerhandbuch
Vol. 3 13-3
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND
To use POPCNT instruction, software must check CPUID.1:ECX.POPCNT[bit 23] = 1
13.1.3
Checking for Support for the FXSAVE and FXRSTOR
Instructions
A separate check must be made to insure that the processor supports FXSAVE and
FXRSTOR. Make sure:
FXRSTOR. Make sure:
•
CPUID.1:EDX.FXSR[bit 24] = 1
13.1.4
Initialization of the SSE/SSE2/SSE3/SSSE3/SSE4 Extensions
The operating system or executive should carry out the following steps to set up
SSE/SSE2/SSE3/SSSE3/SSE4 extensions for use by application programs:
1. Set CR4.OSFXSR[bit 9] = 1. Setting this flag assumes that the operating system
SSE/SSE2/SSE3/SSSE3/SSE4 extensions for use by application programs:
1. Set CR4.OSFXSR[bit 9] = 1. Setting this flag assumes that the operating system
provides facilities for saving and restoring SSE/SSE2/SSE3/SSSE3/SSE4 states
using FXSAVE and FXRSTOR instructions. These instructions are commonly used
to save the SSE/SSE2/SSE3/SSSE3/SSE4 state during task switches and when
invoking the SIMD floating-point exception (#XM) handler (see Section 13.4,
“Saving the SSE/SSE2/SSE3/SSSE3/SSE4 State on Task or Context Switches,”
and Section 13.1.6, “Providing an Handler for the SIMD Floating-Point Exception
(#XM),” respectively).
using FXSAVE and FXRSTOR instructions. These instructions are commonly used
to save the SSE/SSE2/SSE3/SSSE3/SSE4 state during task switches and when
invoking the SIMD floating-point exception (#XM) handler (see Section 13.4,
“Saving the SSE/SSE2/SSE3/SSSE3/SSE4 State on Task or Context Switches,”
and Section 13.1.6, “Providing an Handler for the SIMD Floating-Point Exception
(#XM),” respectively).
If the processor does not support the FXSAVE and FXRSTOR instructions,
attempting to set the OSFXSR flag will cause an exception (#GP) to be
generated.
2. Set CR4.OSXMMEXCPT[bit 10] = 1. Setting this flag assumes that the operating
system provides an SIMD floating-point exception (#XM) handler (see Section
13.1.6, “Providing an Handler for the SIMD Floating-Point Exception (#XM)”).
13.1.6, “Providing an Handler for the SIMD Floating-Point Exception (#XM)”).
NOTE
The OSFXSR and OSXMMEXCPT bits in control register CR4 must be
set by the operating system. The processor has no other way of
detecting operating-system support for the FXSAVE and FXRSTOR
instructions or for handling SIMD floating-point exceptions.
set by the operating system. The processor has no other way of
detecting operating-system support for the FXSAVE and FXRSTOR
instructions or for handling SIMD floating-point exceptions.
3. Clear CR0.EM[bit 2] = 0. This action disables emulation of the x87 FPU, which is
required when executing SSE/SSE2/SSE3/SSSE3/SSE4 instructions (see Section
2.5, “Control Registers”).
2.5, “Control Registers”).
4. Set CR0.MP[bit 1] = 1. This setting is the required setting for Intel 64 and IA-32
processors that support the SSE/SSE2/SSE3/SSSE3/SSE4 extensions (see
Section 9.2.1, “Configuring the x87 FPU Environment”).
Section 9.2.1, “Configuring the x87 FPU Environment”).
Table 13-1 and Table 13-2 show the actions of the processor when an
SSE/SSE2/SSE3/SSSE3/SSE4 instruction is executed, depending on the:
SSE/SSE2/SSE3/SSSE3/SSE4 instruction is executed, depending on the: