Intel 253668-032US Benutzerhandbuch
19-10 Vol. 3
ARCHITECTURE COMPATIBILITY
math coprocessor (flag is clear) or an Intel 387 DX math coprocessor (flag is set).
This bit is hardwired to 1 in the P6 family, Pentium, and Intel486 processors.
The NE (Numeric Exception) flag (bit 5 of the CR0 register) is used in the P6 family,
Pentium, and Intel486 processors to determine whether unmasked floating-point
exceptions are reported internally through interrupt vector 16 (flag is set) or exter-
nally through an external interrupt (flag is clear). On a hardware reset, the NE flag is
initialized to 0, so software using the automatic internal error-reporting mechanism
must set this flag to 1. This flag is nonexistent on the Intel386 processor.
As on the Intel 286 and Intel386 processors, the MP (monitor coprocessor) flag (bit 1
of register CR0) determines whether the WAIT/FWAIT instructions or waiting-type
floating-point instructions trap when the context of the x87 FPU is different from that
of the currently-executing task. If the MP and TS flag are set, then a WAIT/FWAIT
instruction and waiting instructions will cause a device-not-available exception
(interrupt vector 7). The MP flag is used on the Intel 286 and Intel386 processors to
support the use of a WAIT/FWAIT instruction to wait on a device other than a math
coprocessor. The device reports its status through the BUSY# pin. Since the P6
family, Pentium, and Intel486 processors do not have such a pin, the MP flag has no
relevant use and should be set to 1 for normal operation.
This bit is hardwired to 1 in the P6 family, Pentium, and Intel486 processors.
The NE (Numeric Exception) flag (bit 5 of the CR0 register) is used in the P6 family,
Pentium, and Intel486 processors to determine whether unmasked floating-point
exceptions are reported internally through interrupt vector 16 (flag is set) or exter-
nally through an external interrupt (flag is clear). On a hardware reset, the NE flag is
initialized to 0, so software using the automatic internal error-reporting mechanism
must set this flag to 1. This flag is nonexistent on the Intel386 processor.
As on the Intel 286 and Intel386 processors, the MP (monitor coprocessor) flag (bit 1
of register CR0) determines whether the WAIT/FWAIT instructions or waiting-type
floating-point instructions trap when the context of the x87 FPU is different from that
of the currently-executing task. If the MP and TS flag are set, then a WAIT/FWAIT
instruction and waiting instructions will cause a device-not-available exception
(interrupt vector 7). The MP flag is used on the Intel 286 and Intel386 processors to
support the use of a WAIT/FWAIT instruction to wait on a device other than a math
coprocessor. The device reports its status through the BUSY# pin. Since the P6
family, Pentium, and Intel486 processors do not have such a pin, the MP flag has no
relevant use and should be set to 1 for normal operation.
19.18.2 x87 FPU Status Word
This section identifies differences to the x87 FPU status word for the different IA-32
processors and math coprocessors, the reason for the differences, and their impact
on software.
processors and math coprocessors, the reason for the differences, and their impact
on software.
19.18.2.1 Condition Code Flags (C0 through C3)
The following information pertains to differences in the use of the condition code
flags (C0 through C3) located in bits 8, 9, 10, and 14 of the x87 FPU status word.
After execution of an FINIT instruction or a hardware reset on a 32-bit x87 FPU, the
condition code flags are set to 0. The same operations on a 16-bit IA-32 math copro-
cessor leave these flags intact (they contain their prior value). This difference in
operation has no impact on software and provides a consistent state after reset.
Transcendental instruction results in the core range of the P6 family and Pentium
processors may differ from the Intel486 DX processor and Intel 487 SX math copro-
cessor by 2 to 3 units in the last place (ulps)—(see “Transcendental Instruction Accu-
racy” in Chapter 8, “Programming with the x87 FPU,” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1). As a result, the value saved
in the C1 flag may also differ.
After an incomplete FPREM/FPREM1 instruction, the C0, C1, and C3 flags are set to 0
on the 32-bit x87 FPUs. After the same operation on a 16-bit IA-32 math copro-
cessor, these flags are left intact.
flags (C0 through C3) located in bits 8, 9, 10, and 14 of the x87 FPU status word.
After execution of an FINIT instruction or a hardware reset on a 32-bit x87 FPU, the
condition code flags are set to 0. The same operations on a 16-bit IA-32 math copro-
cessor leave these flags intact (they contain their prior value). This difference in
operation has no impact on software and provides a consistent state after reset.
Transcendental instruction results in the core range of the P6 family and Pentium
processors may differ from the Intel486 DX processor and Intel 487 SX math copro-
cessor by 2 to 3 units in the last place (ulps)—(see “Transcendental Instruction Accu-
racy” in Chapter 8, “Programming with the x87 FPU,” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1). As a result, the value saved
in the C1 flag may also differ.
After an incomplete FPREM/FPREM1 instruction, the C0, C1, and C3 flags are set to 0
on the 32-bit x87 FPUs. After the same operation on a 16-bit IA-32 math copro-
cessor, these flags are left intact.