Intel 253668-032US Benutzerhandbuch
Vol. 3 19-11
ARCHITECTURE COMPATIBILITY
On the 32-bit x87 FPUs, the C2 flag serves as an incomplete flag for the FTAN instruc-
tion. On the 16-bit IA-32 math coprocessors, the C2 flag is undefined for the FPTAN
instruction. This difference has no impact on software, because Intel 287 or 8087
programs do not check C2 after an FPTAN instruction. The use of this flag on later
processors allows fast checking of operand range.
tion. On the 16-bit IA-32 math coprocessors, the C2 flag is undefined for the FPTAN
instruction. This difference has no impact on software, because Intel 287 or 8087
programs do not check C2 after an FPTAN instruction. The use of this flag on later
processors allows fast checking of operand range.
19.18.2.2 Stack Fault Flag
When unmasked stack overflow or underflow occurs on a 32-bit x87 FPU, the IE flag
(bit 0) and the SF flag (bit 6) of the x87 FPU status word are set to indicate a stack
fault and condition code flag C1 is set or cleared to indicate overflow or underflow,
respectively. When unmasked stack overflow or underflow occurs on a 16-bit IA-32
math coprocessor, only the IE flag is set. Bit 6 is reserved on these processors. The
addition of the SF flag on a 32-bit x87 FPU has no impact on software. Existing excep-
tion handlers need not change, but may be upgraded to take advantage of the addi-
tional information.
(bit 0) and the SF flag (bit 6) of the x87 FPU status word are set to indicate a stack
fault and condition code flag C1 is set or cleared to indicate overflow or underflow,
respectively. When unmasked stack overflow or underflow occurs on a 16-bit IA-32
math coprocessor, only the IE flag is set. Bit 6 is reserved on these processors. The
addition of the SF flag on a 32-bit x87 FPU has no impact on software. Existing excep-
tion handlers need not change, but may be upgraded to take advantage of the addi-
tional information.
19.18.3 x87 FPU Control Word
Only affine closure is supported for infinity control on a 32-bit x87 FPU. The infinity
control flag (bit 12 of the x87 FPU control word) remains programmable on these
processors, but has no effect. This change was made to conform to the IEEE Stan-
dard 754 for Binary Floating-Point Arithmetic. On a 16-bit IA-32 math coprocessor,
both affine and projective closures are supported, as determined by the setting of bit
12. After a hardware reset, the default value of bit 12 is projective. Software that
requires projective infinity arithmetic may give different results.
control flag (bit 12 of the x87 FPU control word) remains programmable on these
processors, but has no effect. This change was made to conform to the IEEE Stan-
dard 754 for Binary Floating-Point Arithmetic. On a 16-bit IA-32 math coprocessor,
both affine and projective closures are supported, as determined by the setting of bit
12. After a hardware reset, the default value of bit 12 is projective. Software that
requires projective infinity arithmetic may give different results.
19.18.4 x87 FPU Tag Word
When loading the tag word of a 32-bit x87 FPU, using an FLDENV, FRSTOR, or
FXRSTOR (Pentium III processor only) instruction, the processor examines the
incoming tag and classifies the location only as empty or non-empty. Thus, tag
values of 00, 01, and 10 are interpreted by the processor to indicate a non-empty
location. The tag value of 11 is interpreted by the processor to indicate an empty
location. Subsequent operations on a non-empty register always examine the value
in the register, not the value in its tag. The FSTENV, FSAVE, and FXSAVE (Pentium III
processor only) instructions examine the non-empty registers and put the correct
values in the tags before storing the tag word.
The corresponding tag for a 16-bit IA-32 math coprocessor is checked before each
register access to determine the class of operand in the register; the tag is updated
after every change to a register so that the tag always reflects the most recent status
of the register. Software can load a tag with a value that disagrees with the contents
of a register (for example, the register contains a valid value, but the tag says
special). Here, the 16-bit IA-32 math coprocessors honor the tag and do not examine
the register.
FXRSTOR (Pentium III processor only) instruction, the processor examines the
incoming tag and classifies the location only as empty or non-empty. Thus, tag
values of 00, 01, and 10 are interpreted by the processor to indicate a non-empty
location. The tag value of 11 is interpreted by the processor to indicate an empty
location. Subsequent operations on a non-empty register always examine the value
in the register, not the value in its tag. The FSTENV, FSAVE, and FXSAVE (Pentium III
processor only) instructions examine the non-empty registers and put the correct
values in the tags before storing the tag word.
The corresponding tag for a 16-bit IA-32 math coprocessor is checked before each
register access to determine the class of operand in the register; the tag is updated
after every change to a register so that the tag always reflects the most recent status
of the register. Software can load a tag with a value that disagrees with the contents
of a register (for example, the register contains a valid value, but the tag says
special). Here, the 16-bit IA-32 math coprocessors honor the tag and do not examine
the register.