Intel 253668-032US Benutzerhandbuch
Vol. 3 3-3
PROTECTED-MODE MEMORY MANAGEMENT
storage. When using paging, each segment is divided into pages (typically 4 KBytes
each in size), which are stored either in physical memory or on the disk. The oper-
ating system or executive maintains a page directory and a set of page tables to keep
track of the pages. When a program (or task) attempts to access an address location
in the linear address space, the processor uses the page directory and page tables to
translate the linear address into a physical address and then performs the requested
operation (read or write) on the memory location.
If the page being accessed is not currently in physical memory, the processor inter-
rupts execution of the program (by generating a page-fault exception). The oper-
ating system or executive then reads the page into physical memory from the disk
and continues executing the program.
When paging is implemented properly in the operating-system or executive, the
swapping of pages between physical memory and the disk is transparent to the
correct execution of a program. Even programs written for 16-bit IA-32 processors
can be paged (transparently) when they are run in virtual-8086 mode.
each in size), which are stored either in physical memory or on the disk. The oper-
ating system or executive maintains a page directory and a set of page tables to keep
track of the pages. When a program (or task) attempts to access an address location
in the linear address space, the processor uses the page directory and page tables to
translate the linear address into a physical address and then performs the requested
operation (read or write) on the memory location.
If the page being accessed is not currently in physical memory, the processor inter-
rupts execution of the program (by generating a page-fault exception). The oper-
ating system or executive then reads the page into physical memory from the disk
and continues executing the program.
When paging is implemented properly in the operating-system or executive, the
swapping of pages between physical memory and the disk is transparent to the
correct execution of a program. Even programs written for 16-bit IA-32 processors
can be paged (transparently) when they are run in virtual-8086 mode.
3.2 USING
SEGMENTS
The segmentation mechanism supported by the IA-32 architecture can be used to
implement a wide variety of system designs. These designs range from flat models
that make only minimal use of segmentation to protect programs to multi-
segmented models that employ segmentation to create a robust operating environ-
ment in which multiple programs and tasks can be executed reliably.
The following sections give several examples of how segmentation can be employed
in a system to improve memory management performance and reliability.
implement a wide variety of system designs. These designs range from flat models
that make only minimal use of segmentation to protect programs to multi-
segmented models that employ segmentation to create a robust operating environ-
ment in which multiple programs and tasks can be executed reliably.
The following sections give several examples of how segmentation can be employed
in a system to improve memory management performance and reliability.
3.2.1
Basic Flat Model
The simplest memory model for a system is the basic “flat model,” in which the oper-
ating system and application programs have access to a continuous, unsegmented
address space. To the greatest extent possible, this basic flat model hides the
segmentation mechanism of the architecture from both the system designer and the
application programmer.
To implement a basic flat memory model with the IA-32 architecture, at least two
segment descriptors must be created, one for referencing a code segment and one
for referencing a data segment (see Figure 3-2). Both of these segments, however,
are mapped to the entire linear address space: that is, both segment descriptors
have the same base address value of 0 and the same segment limit of 4 GBytes. By
setting the segment limit to 4 GBytes, the segmentation mechanism is kept from
generating exceptions for out of limit memory references, even if no physical
memory resides at a particular address. ROM (EPROM) is generally located at the top
of the physical address space, because the processor begins execution at
ating system and application programs have access to a continuous, unsegmented
address space. To the greatest extent possible, this basic flat model hides the
segmentation mechanism of the architecture from both the system designer and the
application programmer.
To implement a basic flat memory model with the IA-32 architecture, at least two
segment descriptors must be created, one for referencing a code segment and one
for referencing a data segment (see Figure 3-2). Both of these segments, however,
are mapped to the entire linear address space: that is, both segment descriptors
have the same base address value of 0 and the same segment limit of 4 GBytes. By
setting the segment limit to 4 GBytes, the segmentation mechanism is kept from
generating exceptions for out of limit memory references, even if no physical
memory resides at a particular address. ROM (EPROM) is generally located at the top
of the physical address space, because the processor begins execution at