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1

Writing a 11b to the Power State field of the Power Management Control/Status Register (PMCSR) transitions 
the Ethernet controller to D3.

2

The system can keep the Ethernet controller in D3 state for an arbitrary amount of time.

3

To exit D3 state the system writes 00b to the Power State field of the Power Management Control/Status 
Register (PMCSR).

4

APM Wakeup mode can be enabled based on what is read in the EEPROM.

5

For the 82544GC/EI, PWR_STATE[1:0] is set to 01b if APM Wakeup is enabled, 00b otherwise.

6

The system can delay an arbitrary time before enabling memory access.

7

Writing a 1b to the Memory Access Enable or I/O Access Enable bit in the PCI Command Register transitions 
the Ethernet controller from D0u to D0 state.
For the 82544GC/EI, writing a 1b to the Memory Access Enable or I/O Access Enable bit in the PCI Command 
Register transitions the Ethernet controller from D0u to D0 state and asserts both PWR_STATE outputs.