Renesas R5S72622 Benutzerhandbuch

 

Section 18   Serial Sound Interface 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 931 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

Yes

No

No

Yes

Yes

No

TUIEN = 1, TOIEN = 1, TIE = 1,
TEN = 1

TEN = 0, 
TUIEN = 0, TOIEN = 0, 
IIEN = 1, TIE = 0

Start

Release from reset, 

set SSICR configuration bits.

Set up the direct memory

access controller.

Enable the direct memory

access controller.

Enable error interrupts

and transmit interrupts,

then enable transmission.

Wait for an interrupt.

Wait for more than 

1.5 cycles of SSIWS.

Disable transmit operation.

(TEN = 0)

Wait for more than 

one cycle of SSISCK.

Enable transmit operation agan.

(TEN = 1)

Error interrupt?

Yes

No

IDST = 1?

End of DMA transfer?

More data to be sent?

Disable transmit operation,*

2

disable direct memory access 

controller, 

disable an error interrupt, 

enable an idle interrupt.

Wait for an idle interrupt 

from this module

End*

1

Notes:  Transmission may not start if the specified procedure is not followed.
 

  1.  If an error interrupt (underflow/overflow) occurs, go back to 

 

   

the start in the flowchart again. 

  

2. 

When restarting transmission after disabling transmit operation (TEN = 0),

 

   

first apply a software reset before going back to start in the flowchart.

Define SCKD, SWSD, MUEN, 
DEL, PDTA, SDTA, SPDP, 
SWSP, SCKP, SWL, DWL, 
CHNL