Integral INAFM8G40VMXB Benutzerhandbuch
5
43*
GND
44*
NC
* Note: Pin 41~44 only for 44pin AFM
2.2 Pin Description
Pin No.
Signal
I/O* Description
01
-RESET
I
Hardware reset signal from the host
17,15,13,11,09,07,
05,03,04,06,08,10,
12,14,16,18
DD0~DD15(Device Data)
I/O
16-bit bi-direction Data Bus. DD(7:0) are
used for 8-bit register transfers.
21
DMARQ(DMA Request)
O
For DMA data transfers. Device will
assert DMARQ when the device is ready
to transfer data to or from the host.
23
-DIOW(I/O Write)
I
This is the strobe signal used by the host
to write to the device register or Data port
STOP(Stop UDMA Burst)
The host assert this signal during an
UDMA burst to stop the DMA burst
25
IORDY(I/O channel ready)
O
This signal is used to temporarily stop
the host register access (read or write)
when the device is not ready to respond
to a data transfer request.
DDMARDY(UDMA ready)
The device will assert this signal to
indicate that the device is ready to receive
UDMA data-out burst.
DSTROBE(UDMA data
strobe)
When UDMA mode DMA Read is active,
this signal is the data-in strobe generated
by the device.
28
CSEL(Cable select)
I
This pin is used to configure this device
as Device 0 or Device 1.
29
-DMACK(DMA
I
This signal is used by the host in respond