Integral INAFM8G40VMXB Benutzerhandbuch
6
acknowledge)
to DMARQ to initiate DMA transfer.
31
INTRQ(Interrupt)
O
When this device is selected, this signal is
the active high Interrupt Request to the
host
Pin No.
Signal
I/O Description
32
IOIS16
O
During PIO transfer mode0,1or 2, this pin
indicates to the host the 16-bit data port has
been addressed and the device is prepared
to send or receive a 16-bit data word.
When transferring in DMA mode, the host
must use a 16-bit DMA channel and this
signal will not be asserted.
35, 33, 36
DA0~DA2(Device Address)
I
This is 3-bit binary coded Address Bus.
34
-PDIAG(Passed diagnostics)
I/O
This signal will be asserted by Device 1 to
indicate to Device 0 that Device 1 has
completed diagnostics,
-CBLID(Cable assembly
type identify)
37, 38
-CS0, -CS1(Chip select)
I
These signals are used to select the
Command Block and Control Block
registers. When –DMACK is asserted, -Cs0
and –Cs1 shall be negated and transfers
shall be 16-bit wide.
39
-DASP(Device active, Device
1 present)
I/O
During the reset protocol, -DASP shall be
asserted by Device 1 to indicate that the
device is present.
41*, 42*
VCC
P
Power supply
02, 19, 22, 24, 26, 30,
40, 43*
GND
--
Ground.
*Note:
“I”
An input from the host system to the device.
“O”
An output from the device to the host system.
“I/O”
An input/output(bi-direction) common.
“P”
Power supply.