Cisco Cisco UCS B22 M3 Blade Server Datenbogen

The DIMM and CPU layout is shown in 

.

Each CPU controls four memory channels, and each memory channel controls two subchannels each through 
individual memory buffers placed around the motherboard (shown as black rectangles on 

). Each 

subchannel controls 3 DIMMs as follows (refer also to 

):

■

CPU 1 subchannels A through H and DIMMs controlled:

— A1 (blue DIMM slot), A2 (black DIMM slot), A3 (white DIMM slot)

— B1 (blue DIMM slot), B2 (black DIMM slot), B3 (white DIMM slot)

— C1 (blue DIMM slot), C2 (black DIMM slot), C3 (ivory DIMM slot)

— D1 (blue DIMM slot), D2 (black DIMM slot), D3 (ivory DIMM slot)

— E1 (blue DIMM slot), E2 (black DIMM slot), E3 (ivory DIMM slot)

A1 A2 A3

B1 B2 B3

C1 C2 C3

D1 D2 D3

F3 F2 F1

E3 E2 E1

G1 G2 G3

H1 H2 H3

J3 J2 J1

I3 I2 I1

L3 L2 L1

K3 K2 K1

P3 P2 P1

O3

CPU 1

CPU 2

O2 O1

M1M2 M3

N1 N2 N3

CPU 1 DIMMs

CPU 2 DIMMs

CPU 1 DIMMs

CPU 2 DIMMs

CPU 1 DIMMs

CPU 2 DIMMs