Nokia 9210i Servicehandbuch

PAMS

Technical Documentation

RAE-5 

3. RF+System Module KL8 

Page 3 – 30

Issue 1 04/02

In following chapters the blocks of system HW in SYSTEM part of KL8 sche-
matics and functions related to each interface are described.

The blocks include: CPU, MEMORIES, MMC, IRDA, UI, SYSCON, AUDIO_RFI
and POWER.

Component placement diagrams are in the A3 section.

Main components in the CPU block comprise:
– MADLinda ASIC (D300), package 240 

m*

BGA

– Hall switch TLE4916 (V301)

MADLinda is the main ASIC for RAE-5’s single processor system. MADLinda is
used as engine processor for both CMT and PDA functions.  The pins are not
listed because it is not possible to access them except at measurement points.

Hall sensor switch is used to detect lid position (open/close). Magnet for detec-
tion is in lid part of RAE-5. Hall device’s open drain output is pulled up with ex-
ternal 100k

W

 resistor (R302). Output goes to low state when the sensor is not in

magnetic field (lid open).

Main components in the block are:
– two 4Mx16 (64Mbit) Flash memories (D351, D352) 
– DOC 16MB (128Mbit) flash memory (D353)
– SDRAM 4Mx16 (64Mbit) (D350);  
– Serial Flash 32Mbit (D354);  – Serial flash is not assembled to kl8  module

The directly executable MPU program code resides in two XIP Flash memories.

In Assembled device when 1.8V IO–line is connected to VPP –pins, Flash de-
vices consider the high level as program enable and actual programming cur-
rent is taken from Vcc pin of Flash. Vpp connection scheme is shown in
Figure 7.

Reset state of MPUGenIO1 protection signal is low so writing/programming is
initially disabled.

Flashes are 8Mbyte (4Mx16) 70ns/52MHz synchronous burst mode devices
packed in 56 pin CSP (

m

BGA56).

XIP memories are fully supplied from 1.8V Vcore voltage.