FIC a440 Servicehandbuch
Hardware Functional Overview
4-6
FIC A440 Series Service Manual
- 66 / 100 / 133MHz CPU Front Side Bus (FSB) Operation
• High Integration
- Single chip implementation for 64-bit Slot-1 and Socket-370 CPUs, 64-bit system
memory, 32-bit PCI with integrated 2D / 3D GUI accelerator
- Apollo ProMedia Chipset: VT8601 system controller and VT82C686A PCI to
ISA bridge
- Chipset includes dual UltraDMA-33/66 EIDE, AC-97 link, 4 USB ports,
integrated Super-I/O, hardware monitoring, keyboard/mouse interfaces, and
RTC/CMOS
RTC/CMOS
• High Performance CPU Interface
- Supports Slot-1 Intel Pentium II / Pentium III and Socket 370 Celeron processors
- 66 / 100 / 133 MHz CPU Front Side Bus (FSB)
- Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and
- 66 / 100 / 133 MHz CPU Front Side Bus (FSB)
- Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and
between clocking regions
- Five outstanding transactions (four In-Order Queue (IOQ) plus one input latch)
- Supports WC (Write Combining) cycles
- Dynamic deferred transaction support
- Sleep mode support
- System management interrupt, memory remap and STPCLK mechanism
- Supports WC (Write Combining) cycles
- Dynamic deferred transaction support
- Sleep mode support
- System management interrupt, memory remap and STPCLK mechanism
• Internal Accelerated Graphics Port (AGP) Controller
- AGP v1.0 compliant
- Pipelined split-transaction long-burst transfers up to 533 MB/sec
- Eight level posted-write request queue
- Thirty-two level (quadwords) read data FIFO (128 bytes)
- Sixteen level (quadwords) write data FIFO (64 bytes)
- Intelligent request reordering for maximum AGP bus utilization
- Supports Flush/Fence commands
- Graphics Address Relocation Table (GART)
- Independent GART lookup control for host / AGP / PCI master accesses
- Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver
- Pipelined split-transaction long-burst transfers up to 533 MB/sec
- Eight level posted-write request queue
- Thirty-two level (quadwords) read data FIFO (128 bytes)
- Sixteen level (quadwords) write data FIFO (64 bytes)
- Intelligent request reordering for maximum AGP bus utilization
- Supports Flush/Fence commands
- Graphics Address Relocation Table (GART)
- Independent GART lookup control for host / AGP / PCI master accesses
- Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver
support
• Concurrent PCI Bus Controller
- PCI Bus is synchronous / pseudo-synchronous to host CPU bus
- 33 MHz operation on the primary PCI bus
- Supports up to five PCI masters
- Concurrent multiple PCI master transactions
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132MB/sec
- Six levels (double-words) of CPU to PCI posted write buffers
- Enhanced PCI command optimization
- Delay transaction from PCI master reading DRAM
- Complete steerable PCI interrupts
- PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
- 33 MHz operation on the primary PCI bus
- Supports up to five PCI masters
- Concurrent multiple PCI master transactions
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132MB/sec
- Six levels (double-words) of CPU to PCI posted write buffers
- Enhanced PCI command optimization
- Delay transaction from PCI master reading DRAM
- Complete steerable PCI interrupts
- PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
• Advanced High Performance DRAM Controller
- DRAM interface synchronous or pseudo-synchronous with CPU FSB speed of 66
/ 100 / 133 MHz
- Concurrent CPU, AGP, and PCI access
- Supports FP, EDO, SDRAM and VCM-SDRAM memory types
- 64-bit data width only
- 3.3V DRAM interface with 5V-tolerant inputs
- Supports FP, EDO, SDRAM and VCM-SDRAM memory types
- 64-bit data width only
- 3.3V DRAM interface with 5V-tolerant inputs
• General Graphics Capabilities
- 64-bit Single Cycle 2D/3D Graphics Engine