Intel 41210 Benutzerhandbuch
Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
103
Register Description
12.2.49
Offset E4h: PX_DSTC—PCI-X Downstream Split
Transaction Control
Transaction Control
This register controls the behavior of the 41210 buffers for forwarding split transactions from PCI
Express* to the secondary bus.
Express* to the secondary bus.
Table 83.
Offset E4h: PX_DSTC—PCI-X Downstream Split Transaction Control
Bits
Type
Reset
Description
31:16
RW
FFFFh
Split Transaction Limit (STL):
This field is R/W to accommodate diagnostic software that
might want to use it. The field is not used by the Intel
®
41210 Serial to Parallel PCI Bridge
for modifying its “commitment” level. The 41210 internal launch algorithms prevent buffers
from being over-allocated.
from being over-allocated.
15:0
RO
FFFFh
Split Transaction Capacity (STC):
Due to the internal launch algorithm, the 41210 always
has capacity for its outstanding split transactions.