Benutzerhandbuch für Intel 41210

Inhaltsverzeichnis

• Intel® 41210 Serial to Parallel PCI Bridge

  1
  • Copyright

    2
  • Contents

    3
  • Revision History

    10
• Introduction 1

  11
  • 1.1 PCI Express* Interface Features

    11
  • 1.2 PCI-X Interface Features

    11
  • 1.3 Power Management

    12
  • 1.4 SMBus Interface

    12
  • 1.5 JTAG

    12
• Signal Description 2

  13
  • 2.1 On-Die Termination (ODT)

    13
  • 2.2 PCI Express* Interface

    15
  • 2.3 PCI Bus Interface (Two Instances)

    16
  • 2.4 PCI Bus Interface 64-Bit Extension (Two Interfaces)

    18
  • 2.5 PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces)

    18
  • 2.6 Interrupt Interface (Two Interfaces)

    19
  • 2.7 Reset Straps

    20
  • 2.8 SMBus Interface

    21
  • 2.9 Miscellaneous Pins

    22
  • 2.10 Voltage Pins

    23
• PCI-X Interface 3

  25
  • 3.1 Initialization

    25
  • 3.2 Transactions Supported

    26
    • 3.2.1 PCI Mode

      26
    • 3.2.2 PCI-X Mode

      27
    • 3.2.3 Read Transactions

      27
    • 3.2.4 Configuration Transactions

      28
    • 3.2.5 LOCK Cycles

      29
    • 3.2.6 Decoding

      30
    • 3.2.7 Transaction Termination

      30
  • 3.3 PCI-X Protocol Specifics

    34
    • 3.3.1 Attributes

      34
    • 3.3.2 4 GB and 4 K Page Crossover

      34
    • 3.3.3 Wait States

      34
    • 3.3.4 Split Transactions

      35
  • 3.4 Arbitration

    35
• Power Management 4

  37
  • 4.1 Hardware-Controlled Active State Power Management

    37
  • 4.2 Software-Driven PCI-PM 1.1-Compatible Power Management

    37
  • 4.3 PCI Bus Power Management

    37
  • 4.4 Intel® 41210 Serial to Parallel PCI Bridge Device Power Management

    38
  • 4.5 Power-Management Event Signaling

    38
• Addressing 5

  41
  • 5.1 Addressable Spaces within the Intel® 41210 Serial to Parallel PCI Bridge

    41
  • 5.2 Secondary PCI Devices

    42
  • 5.3 Configuration-Space Access

    42
    • 5.3.1 PCI Express* Configuration Access

      42
    • 5.3.2 Type 0 Configuration Access from PCI-X Interface

      44
    • 5.3.3 SMBus Configuration Access

      45
  • 5.4 I/O Space Access Mechanism

    45
  • 5.5 Memory Space Access Mechanism

    47
    • 5.5.1 Memory-Mapped I/O Window

      48
    • 5.5.2 Prefetchable Memory Window

      49
    • 5.5.3 Opaque Memory Window

      49
  • 5.6 VGA Addressing

    49
• Transaction Ordering 6

  51
  • 6.1 Upstream Transaction Ordering

    51
  • 6.2 Downstream Transaction Ordering

    52
  • 6.3 Relaxed Ordering/No-Snoop Support

    52
• Interrupt Support 7

  53
  • 7.1 Legacy Interrupt Sharing

    53
  • 7.2 Interrupt Routing for Devices behind a Bridge

    54
• System Management Bus Interface 8

  55
  • 8.1 SMBus Commands

    56
  • 8.2 Initialization Sequence

    57
    • 8.2.1 Configuration

      57
    • 8.2.2 Configuration Writes

      60
  • 8.3 Error Handling

    61
  • 8.4 SMBus Interface Reset

    62
• Local Initialization 9

  63
• Clock and Reset 10

  65
  • 10.1 Clocking

    65
  • 10.2 Device Reset

    65
    • 10.2.1 PERST# Reset Mechanism

      66
    • 10.2.2 RSTIN# Reset Mechanism

      66
    • 10.2.3 PCI Express* Reset Mechanism

      66
    • 10.2.4 Software PCI Reset (SBR-Secondary Bus Reset)

      67
• Error Handling 11

  69
  • 11.1 PCI Express* Errors

    69
  • 11.2 PCI Errors

    69
    • 11.2.1 Error Types

      70
    • 11.2.2 Termination of Completion Required Transactions

      70
• Register Description 12

  73
  • 12.1 Register Nomenclature and Access Attributes

    73
  • 12.2 Configuration Registers

    74
    • 12.2.1 Offset 00h: ID-Identifiers

      78
    • 12.2.2 Offset 04h: PCICMD-Command Register

      78
    • 12.2.3 Offset 06h: PSTS-Primary Device Status

      79
    • 12.2.4 Offset 08h: REVID-Revision ID

      80
    • 12.2.5 Offset 09h: CC-Class Code

      81
    • 12.2.6 Offset 0Ch: CLS-Cache-Line Size

      81
    • 12.2.7 Offset 0Dh: PMLT-Primary Master Latency Timer

      81
    • 12.2.8 Offset 0Eh: HEADTYP-Header Type

      81
    • 12.2.9 Offset 18h: BNUM-Bus Numbers

      82
    • 12.2.10 Offset 1Bh: SMLT-Secondary Master Latency Timer

      82
    • 12.2.11 Offset 1Ch: IOBL-I/O Base and Limit

      83
    • 12.2.12 Offset 1Eh: SSTS-Secondary Status

      84
    • 12.2.13 Offset 20h: MBL-Memory Base and Limit

      85
    • 12.2.14 Offset 24h: PMBL-Prefetchable Memory Base and Limit

      86
    • 12.2.15 Offset 28h: PMBU32-Prefetchable Memory Base Upper 32 Bits

      86
    • 12.2.16 Offset 2Ch: PMLU32-Prefetchable Memory Limit Upper 32 Bits

      87
    • 12.2.17 Offset 30h: IOBLU16-I/O Base and Limit Upper 16 Bits

      87
    • 12.2.18 Offset 34h: CAPP-Capabilities List Pointer

      87
    • 12.2.19 Offset 3Ch: INTR-Interrupt Information

      87
    • 12.2.20 Offset 3Eh: BCTRL-Bridge Control

      88
    • 12.2.21 Offset 40h: BCNF-Bridge Configuration Register

      90
    • 12.2.22 Offset 42h: MTT-Multi-Transaction Timer

      91
    • 12.2.23 Offset 43h: PCLKC-PCI Clock Control

      91
    • 12.2.24 Offset 44h: EXP_CAPID-PCI Express* Capability Identifier

      91
    • 12.2.25 Offset 45h: EXP_NXTP-Next Item Pointer

      91
    • 12.2.26 Offset 46h: EXP_CAP-PCI Express* Capability

      92
    • 12.2.27 Offset 48h: EXP_DCAP-PCI Express* Device Capabilities Register

      92
    • 12.2.28 Offset 4Ch: EXP_DCTL-PCI Express* Device Control Register

      93
    • 12.2.29 Offset 4Eh: EXP_DSTS-PCI Express* Device Status Register

      94
    • 12.2.30 Offset 50h: EXP_LCAP-PCI Express* Link Capabilities Register

      94
    • 12.2.31 Offset 54h: EXP_LCTL-PCI Express* Link Control Register

      95
    • 12.2.32 Offset 56h: EXP_LSTS-PCI Express* Link Status Register

      96
    • 12.2.33 Offset 5Ch: MSI_CAPID-PCI Express* MSI Capability Identifier

      96
    • 12.2.34 Offset 5Dh: MSI_NXTP-PCI Express* Next Item Pointer

      96
    • 12.2.35 Offset 5Eh: MSI_MC-PCI Express* MSI Message Control

      97
    • 12.2.36 Offset 60h: MSI_MA-PCI Express* MSI Message Address

      97
    • 12.2.37 Offset 68h: MSI_MD-PCI Express* MSI Message Data

      97
    • 12.2.38 Offset 6Ch: PM_CAPID-Power Management Capabilities Identifier

      97
    • 12.2.39 Offset 6Dh: PM_NXTP-Power Management Next Item Pointer

      98
    • 12.2.40 Offset 6Eh: PM_PMC-Power Management Capabilities

      98
    • 12.2.41 Offset 70h: PM_PMCSR-Power Management Control/Status Register

      99
    • 12.2.42 Offset 72h: PM_BSE-Power Management Bridge Support Extensions

      99
    • 12.2.43 Offset 73h: PM_DATA-Power Management Data Field

      99
    • 12.2.44 Offset D8h: PX_CAPID-PCI-X Capabilities Identifier

      100
    • 12.2.45 Offset D9h: PX_NXTP-PCI-X Next Item Pointer

      100
    • 12.2.46 Offset DAh: PX_SSTS-PCI-X Secondary Status

      101
    • 12.2.47 Offset DCh: PX_BSTS-PCI-X Bridge Status

      102
    • 12.2.48 Offset E0h: PX_USTC-PCI-X Upstream Split Transaction Control

      102
    • 12.2.49 Offset E4h: PX_DSTC-PCI-X Downstream Split Transaction Control

      103
    • 12.2.50 Offset FCh: BINIT-Bridge Initialization Register

      104
    • 12.2.51 Offset 100h: EXPAERR_CAPID-PCI Express* Advanced Error Capability Identifier

      105
    • 12.2.52 Offset 104h: ERRUNC_STS-PCI Express* Uncorrectable Error Status Register

      105
    • 12.2.53 Offset 108h: ERRUNC_MSK-PCI Express* Uncorrectable Error Mask

      106
    • 12.2.54 Offset 10Ch: ERRUNC_SEV-PCI Express* Uncorrectable Error Severity

      107
    • 12.2.55 Offset 110h: ERRCOR_STS-PCI Express* Correctable Error Status

      108
    • 12.2.56 Offset 114h: ERRCOR_MSK-PCI Express* Correctable Error Mask

      109
    • 12.2.57 Offset 118h: ADVERR_CTL-Advanced Error Control and Capability Register

      109
    • 12.2.58 Offset 11C-12Bh: HDR_LOG-PCI Express* Transaction Header Log

      110
    • 12.2.59 Offset 12Ch: PCIXERRUNC_STS-Uncorrectable PCI-X Status Register

      111
    • 12.2.60 Offset 130h: PCIXERRUNC_MSK-Uncorrectable PCI-X Error Mask Register

      113
    • 12.2.61 Offset 134h: PCIXERRUNC_SEV-Uncorrectable PCI-X Error Severity Register

      115
    • 12.2.62 Offset 138h: PCIXERRUNC_PTR-Uncorrectable PCI-X Error Pointer

      116
    • 12.2.63 Offset 13C-14Bh: PCIXHDR_LOG-Uncorrectable PCI-X Error Transaction Header Log

      117
    • 12.2.64 Offset 16Ah: ARB_CNTRL-Internal Arbiter Control Register

      117
    • 12.2.65 Offset 170h: SSR-Strap Status Register

      118
    • 12.2.66 Offset 178h: PREFCTRL-Prefetch Control Register

      119
    • 12.2.67 Offset 300h: PWRBGT_CAPID-Power Budgeting Enhanced Capability Header

      120
    • 12.2.68 Offset 304h: PWRBGT_DSEL-Power Budgeting Data Select Register

      120
    • 12.2.69 Offset 308h: PWRBGT_DATA-Power Budgeting Data Register

      120