Falcom GmbH 051-1-1 Benutzerhandbuch

Description

GPS receiver

A2D–JP

Version 1.03

Side 26

In this state, a portion of the GPS receiver's RF circuitry is de-ener-
gized, the SRAMs are transitioned into their low power data reten-
tion state, and the RTC device is maintained. When the GPS recei-
ver is placed into this low power state through the use of the M_RST 
control signal, the GPS receiver will continue to draw current from 
the primary input power (PWRIN) but at a reduced level.

When the M_RST signal is subsequently asserted high by the OEM, 
RF power is re-applied, a system reset is generated, and the GPS 
receiver will return to its normal Operate mode.

The GPS receiver provides four General Purpose Input/Output 
(GPIO) connections that are available for use by the OEM.
These GPIO connections are digital interfaces that are OEM soft-
ware programmable as inputs or outputs.

The Time Mark output provides a one pulse-per-second (1 pps) 
signal to the OEM application processor. When the GPS receiver 
provides a valid navigation solution, the rising edge of each TMARK 
pulse is synchronized with the UTC one second epochs to within 
±300 nsec.

This is a 10 kHz clock waveform that is synchronized to the UTC 
TMARK pulse.
This clock signal is a positive logic, buffered CMOS level output.

PWRIN 3

Main power input to the JP2 (+3,3 V DC)

3,135 to 3,465

volts

VIH (min)

Minimum high-level input voltage

0.7 x PWRIN

volts

VIH (max)

Maximum high-level input voltage

PWRIN

volts

VIL (min)

Minimum low-level input voltage

- 0,3

volts

VIL (max)

Maximum low-level input voltage

0,3 x PWRIN

volts

VOH (min)

Minimum high-level output voltage

0,8 x PWRIN

volts

VOH (max)

Maximum high-level output voltage

PWRIN

volts