Falcom GmbH 051-1-1 Benutzerhandbuch

Description

GPS receiver

A2D–JP

Version 1.03

Side 27

The host port consists of a full-duplex asynchronous serial data in-
terface. Both binary and NMEA initialization and configuration data 
messages are transmitted and received across this port.

The default ROM settings for the host serial data port are binary 
message format, 9600 baud, no parity, 8 data bits, and 1 stop bit. 
The default may be modified using custom OEM software.
The serial port settings may also be changed to a new configuration 
using binary serial message 1330. The new serial port settings are 
stored in SRAM and serial EEPROM. The next time the GPS recei-
ver is powered on or a master reset is initiated, the serial port confi-
guration parameters are accessed in the following priority:

1.

If SRAM checksums are valid, the communication parameters 
and initialization data parameters will be read from SRAM.

2.

If SRAM checksums are invalid and EEPROM checksums are 
valid, the communication parameters and initialization data 
parameters will be read from EEPROM.

3.

If SRAM checksums are invalid and EEPROM checksums are 
invalid, the default values in ROM will be used.

The OEM application must provide any Line Driver/Line Receiver 
(LD/LR) circuitry to extend the range of the interface.
Port Idle is nominally a CMOS logical high (+ 3,3 V DC).

The auxiliary port consists of a second half-duplex asynchronous 
serial data interface. This port is configured to receive RTCM DGPS 
correction data messages.
The default ROM settings for the Auxiliary Serial Data Port are 9600 
baud, no parity, 8 data bits, and 1 stop bit. The default may be mo-
dified using custom OEM software.

The serial port settings may also be changed to a new configuration 
using binary serial message 1330. The new serial port settings are 
stored in SRAM and serial EEPROM. The next time the GPS recei-
ver is powered on or a master reset is initiated, the serial port confi-
guration parameters are accessed in the following priority:
1.

If SRAM checksums are valid, the communication parameters 
and initialization data parameters will be read from SRAM.

VOL (min)

Minimum low-level output voltage

0

volts

VOL (max)

Maximum low-level output voltage

0,2 x PWRIN

volts

tr, tf

Input rise and fall time

50

nanoseconds

C out

Maximum output load capacitance

25

picofarads

(*) PWRIN refers to a + 3,3 V DC power input (PWRIN-3)