E F Johnson Company 2422001-1 Benutzerhandbuch
CIRCUIT DESCRIPTION
6-5
August 2000
Part No. 001-2001-200
6.1.8 BUFFER
A cascode amplifier formed by Q410/Q411 pro-
vides amplification and isolation between the VCO
and Synthesizer. A cascode amplifier is used because
it provides high gain, high isolation and consumes
only a small amount of power. The input signal to this
amplifier is coupled from the VCO RF output on
pin 5. DC blocking and coupling to the VCO is pro-
vided by C455 and to the buffer by C456. Bias for the
amplifier is provided by R442, R445, R446 and R277.
Q411 is a common-emitter amplifier and Q410 is a
common-base with C458 and C457 providing RF
bypass. L405 provides some filtering of the cascode
output. R448 lowers the Q of L405. The output of the
amplifier is coupled by C442/C441 to U401, pin 11.
and Synthesizer. A cascode amplifier is used because
it provides high gain, high isolation and consumes
only a small amount of power. The input signal to this
amplifier is coupled from the VCO RF output on
pin 5. DC blocking and coupling to the VCO is pro-
vided by C455 and to the buffer by C456. Bias for the
amplifier is provided by R442, R445, R446 and R277.
Q411 is a common-emitter amplifier and Q410 is a
common-base with C458 and C457 providing RF
bypass. L405 provides some filtering of the cascode
output. R448 lowers the Q of L405. The output of the
amplifier is coupled by C442/C441 to U401, pin 11.
6.1.9 SYNTHESIZER
The inputs/outputs of synthesizer U401 are
shown in Figure 6-4. The output signal from the syn-
thesizer loop is the receiver first injection frequency.
This signal is produced by a VCO (voltage-controller
oscillator). The frequency of this oscillator is con-
trolled by a DC voltage. This DC voltage is generated
by integrating the pulses from the phase detector in
synthesizer chip U401.
thesizer loop is the receiver first injection frequency.
This signal is produced by a VCO (voltage-controller
oscillator). The frequency of this oscillator is con-
trolled by a DC voltage. This DC voltage is generated
by integrating the pulses from the phase detector in
synthesizer chip U401.
Frequencies are selected by programming
counters in U401 to divide by a certain number. This
programming is provided through J201, pins 12, 18
and 20. The frequency stability of the synthesizer is
established by the
programming is provided through J201, pins 12, 18
and 20. The frequency stability of the synthesizer is
established by the
±
2.5 PPM stability of TCXO Y401.
The output of this oscillator is stable from
-30
-30
°
C to +60
°
C (-22
°
F to +140
°
F).
Figure 6-4 SYNTHESIZER BLOCK DIAGRAM
(OPEN-DRAIN OUTPUT)
15
OUTPUT B
DATA OUT
24 BITS
A REGISTER
INPUT AMP
PRESCALER
64/65
in
f
in
f
10
11
LOGIC
MODULUS
CONTROL
N COUNTER
12-STAGE
A COUNTER
6-STAGE
CONTROL
INTERNAL
POR
LOGIC
STANDBY
8 BITS
C REGISTER
ENABLE
17
19
DATA IN
CLOCK
18
LOGIC
CONTROL
AND
REGISTER
SHIFT
16 BITS
R REGISTER
DOUBLE-BUFFERED
13-STAGE R COUNTER
DIVIDER
4-STAGE
OSC OR
out
REF
20
in
REF
1
OR (UP)
OV (DOWN)
16
OUTPUT A
LOGIC
SELECT
PORT
V
f
R
f
V
R
2
LOCK DETECT
AND CONTROL
LD
f
f
V
R
f
f
PHASE/FREQUENCY
DETECTOR B
AND CONTROL
PHASE/FREQUENCY
AND CONTROL
DETECTOR A
V
R
f
f
3
4
8
6
Rx
PDout
TEST 2
TEST 1
13
9