Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch

 Processor on 0.13 Micron Process in the 478-Pin Package Datasheet

19

To simplify the following discussion, the system bus signals have been combined into groups by 
buffer type. AGTL+ input signals have differential input buffers that use GTLREF as a reference 
level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the 
AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group 
as well as the AGTL+ I/O group when driving. 

With the implementation of a source synchronous data bus, there is a need to specify two sets of 
timing parameters. One set is for common clock signals which are dependent upon the rising edge 
of BCLK0 (ADS#, HIT#, HITM#, etc.), and the second set is for the source synchronous signals 
that are relative to their respective strobe lines (data and address) as well as the rising edge of 
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at 
any time during the clock cycle. 

 identifies which signals are common clock, source 

synchronous, and asynchronous.

1.

Refer to 

 for signal descriptions.

AGTL+ Common Clock Input

Common Clock 

BPRI#, DEFER#, RESET#

2

, RS[2:0]#, RSP#, TRDY#

2.

These AGTL+ signals do not have on-die termination. Refer to 

 and the appropriate Platform Design

Guide listed in 

 for termination requirements and further details.

AGTL+ Common Clock I/O

Synchronous 

AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#

, BR0#

, 

DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR# 

AGTL+ Source Synchronous 
I/O

Source 
Synchronous 

REQ[4:0]#, A[16:3]#

3

ADSTB0#

A[35:17]#

ADSTB1#

D[15:0]#, DBI0# 

DSTBP0#, DSTBN0#

D[31:16]#, DBI1# 

DSTBP1#, DSTBN1#

D[47:32]#, DBI2#

DSTBP2#, DSTBN2#

D[63:48]#, DBI3#

DSTBP3#, DSTBN3#

3.

The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration
options. See 

 for details.

AGTL+ Strobes

Common Clock

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

Asynchronous GTL+ Input

3,4

4.

These signal groups are not terminated by the processor. Refer to 

, the ITP700 Debug Port Design

Guide, and the appropriate Platform Design Guide listed in 

 for termination requirements and further

details

Asynchronous

A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, 
SLP#, STPCLK#

Asynchronous GTL+ Output

 

Asynchronous

FERR#, IERR#, THERMTRIP#, PROCHOT#

TAP Input

 

 

Synchronous 
to TCK

TCK, TDI, TMS, TRST#

TAP Output

Synchronous 
to TCK

 TDO

System Bus Clock

N/A

BCLK[1:0], ITP_CLK[1:0]

5

5.

In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.

Power/Other

N/A

VCC, VCCA, VCCIOPLL, VCCVID, VID[4:0], VSS, VSSA, 
GTLREF[3:0], COMP[1:0], RESERVED, TESTHI[5:0, 12:8], 
ITPCLKOUT[1:0], THERMDA, THERMDC, PWRGOOD, 
SKTOCC#, VCC_SENSE, VSS_SENSE

, 

BSEL[1:0], DBR#