Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch

32

 Datasheet

The following figures are used in conjunction with the AC timing tables, 

 through 

For 

 through 

, the following apply:

1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage 

(V

CROSS

) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal 

timings are referenced at GTLREF at the processor core.

2. All source synchronous AC timings for AGTL+ signals are referenced to their associated 

strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the 
falling edge of their associated data strobe. Source synchronous address signals are referenced 
to the rising and falling edge of their associated address strobe. All source synchronous 
AGTL+ signal timings are referenced at GTLREF at the processor core silicon.

3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V

CROSS

. All 

AGTL+ strobe signal timings are referenced at GTLREF at the processor core silicon.

4. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the 

processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at 0.5*VCC at the 
processor pins.

The circuit used to test the AC specifications is shown in 

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

These parameters are not tested and are based on design simulations.

T65: ITPCLKOUT Delay

400

560

ps

3

3.

This delay is from rising edge of BCLK0 to the falling edge of ITPCLK0.

T66: Slew Rate

2

8

V/ns

T67: ITPCLKOUT[1:0] High Time

3.89

5

6.17

ns

T68: ITPCLKOUT[1:0] Low Time

3.89

5

6.17

ns

420 mils, 50 

Ω

, 169 ps/in.

 2.4 nH

1.2 pF

Rload = 50 

Ω

AC Timings test measurements
made here.

V

CC

V

CC