Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch
Produktcode
KC.53001.CDG
34
Intel
®
Celeron
®
Processor on 0.13 Micron Process in the 478-Pin Package
Datasheet
Electrical Specifications
Figure 9. Differential Clock Crosspoint Specification
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
Vhavg (mV)
250 + 0.5(VHavg – 710)
250 mV
200
250
300
350
400
450
500
550
600
650
Cr
o
s
s
in
g
Po
in
t
(m
V)
550 + 0.5(VHavg – 710)
550 mV
Figure 10. System Bus Common Clock Valid Delay Timings
BCLK0
BCLK1
Common Clock
Signal (@ driver)
Common Clock
Signal (@ receiver)
T0
T1
T2
T
Q
T
R
valid
valid
valid
T
P
T
P
= T10: T
CO
(Data Valid Output Delay)
T
Q
= T11: T
SU
(Common Clock Setup)
T
R
= T12: T
H
(Common Clock Hold Time)