Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch
Produktcode
KC.53001.CDG
Intel
®
Celeron
®
Processor on 0.13 Micron Process in the 478-Pin Package Datasheet
35
Electrical Specifications
Figure 11. System Bus Reset and Configuration Timings
Figure 12. Source Synchronous 2X (Address) Timings
BCLK
Reset
Configuration
A[31:3], SMI#,
INIT#
Valid
Tv = T13 (RESET# pulse width)
Tw = T45 (Reset configuration signals setup time)
Tx = T46 (Reset configuration signals A[31:3], SMI#, and INIT# hold time)
Ty = T47 (Reset configuration signal BR0# hold time)
Tw = T45 (Reset configuration signals setup time)
Tx = T46 (Reset configuration signals A[31:3], SMI#, and INIT# hold time)
Ty = T47 (Reset configuration signal BR0# hold time)
Tx
Tv
Tt
Tw
Ty
Configuration
BR0#
Valid
T
J
BCLK0
BCLK1
ADSTB# (@ driver)
A# (@ driver)
A# (@ receiver)
ADSTB# (@ receiver)
T1
T2
2.5 ns
5.0 ns
7.5 ns
T
H
T
H
T
J
T
N
T
K
T
M
valid
valid
valid
valid
T
H
= T23: Source Sync. Address Output Valid Before Address Strobe
T
J
= T24: Source Sync. Address Output Valid After Address Strobe
T
K
= T27: Source Sync. Input Setup to BCLK
T
M
= T26: Source Sync. Input Hold Time
T
N
= T25: Source Sync. Input Setup Time
T
P
= T28: First Address Strobe to Second Address Strobe
T
S
= T20: Source Sync. Output Valid Delay
T
R
= T31: Address Strobe Output Valid Delay
T
P
T
R
T
S