Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch

88

 Datasheet

The Sleep state is a very low power state in which the processor maintains its context, maintains 
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be 
entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state 
upon the assertion of the SLP# signal. The SLP# pin should be asserted only when the processor is 
in the Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of 
specification and may result in unapproved operation. 

Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will 
cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching 
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) 
are allowed on the system bus while the processor is in Sleep state. Any transition on an input 
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state and held active as specified in 
the RESET# pin specification, the processor will reset itself, ignoring the transition through Stop-
Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and 
STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the 
processor correctly executes the Reset sequence.

Once in the Sleep state, the SLP# pin must be de-asserted if another asynchronous system bus 
event must occur. The SLP# pin has a minimum assertion of one BCLK period.

When the processor is in Sleep state, it will not respond to interrupts or snoop transactions. 

The Thermal Monitor feature helps control the processor temperature by activating the Thermal 
Control Circuit (TCC) when the processor silicon reaches its maximum operating temperature. The 
TCC reduces processor power consumption by modulating (starting and stopping) the internal 
processor core clocks. The Thermal Monitor feature must be enabled for the processor to be 
operating within specifications. The temperature at which Thermal Monitor activates the thermal 
control circuit is not user configurable and is not software visible. Bus traffic is snooped in the 
normal manner, and interrupt requests are latched (and serviced during the time that the clocks are 
on) while the TCC is active.

When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e., TCC is 
active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle 
specific to the processor (typically 30%–50%). Clocks often will not be off for more than 3.0

µ

s 

when the TCC is active. Cycle times are processor speed dependent and will decrease as processor 
core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/
inactive transitions of the TCC when the processor temperature is near its maximum operating 
temperature. Once the temperature has dropped below the maximum operating temperature, and 
the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.

With a properly designed and characterized thermal solution, it is anticipated that the TCC would 
only be activated for very short periods of time when running the most power intensive 
applications. The processor performance impact due to these brief periods of TCC activation is 
expected to be so minor that it would be immeasurable. An under-designed thermal solution that is 
not able to prevent excessive activation of the TCC in the anticipated ambient environment may 
cause a noticeable performance loss, and in some cases may result in a T

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 that exceeds the