Hynix HMT351U7CFR8A-PBT0 Benutzerhandbuch

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and 

strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the 

requirements in table below. The differential input cross point voltage VIX is measured from the actual 

cross point of true and complement signals to the midlevel between of VDD and VSS

V

IX

(CK)

Differential Input Cross Point Voltage 

relative to VDD/2 for CK, CK

-150

150

mV

2

-175

175

mV

1

V

IX

(DQS)

Differential Input Cross Point Voltage 

relative to VDD/2 for DQS, DQS

-150

150

mV

2

1. Extended range for V

IX

 is only allowed for clock and if single-ended clock input signals CK and CK are monotonic 

with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK - 
CK is larger than 3 V/ns.

2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.



(VDD/2) + Vix (Min) - VSEL  

  25mV 

VSEH - ((VDD/2) + Vix (Max))  

  25mV