Intel MFS5000SI MFS5000SIB Benutzerhandbuch

Intel® Compute Module MFS5000SI TPS  

2BFunctional Architecture 

 

TP02301

DIMM D2

DIMM D1

DIMM C2

DIMM C1

DIMM B2

DIMM B1

DIMM A2

DIMM A1

Branch 0

MCH

Channel A

Channel B

Channel D

Channel C

Branch 1

 

Functionally, DIMM slots A2 and B2 could also have been populated instead of DIMM slots C1 and D1. 
However, your system will not achieve equivalent performance. Figure 8 shows the supported DIMM 
configuration that is recommended because it allows both memory branches from the MCH to operate 
independently and simultaneously. FBD bandwidth is doubled when both branches operate in parallel. 

When operating in the mirrored mode, both branches operate in lock step. In mirrored mode, branch 1 
contains a replicate copy of the data in branch 0. The minimum DIMM configuration to support memory 
mirroring is four DIMMs, populated as shown in Figure 8. All four DIMMs must be identical with respect to 
size, speed, and organization.  

To upgrade a four-DIMM mirrored memory configuration, four additional DIMMs must be added to the 
system. All four DIMMs in the second set must be identical to the first.  

The MCH provides DIMM sparing capabilities. Sparing is a RAS feature that involves configuring a DIMM 
to be placed in reserve so it can be used to replace a DIMM that fails. DIMM sparing occurs within a 
given bank of memory and is not supported across branches.  

Two Memory Sparing configurations are supported: 

ƒ

  Single Branch Mode Sparing 

ƒ

  Dual Branch Mode Sparing  

Revision 1.4 

 

13 

Intel order number: E15154-007