Intel MFS5000SI MFS5000SIB Benutzerhandbuch
Produktcode
MFS5000SIB
Appendix A: Integration and Usage Tips
Intel® Compute Module MFS5000SI TPS
Appendix A: Integration and Usage Tips
When two processors are installed, both must be of identical revision, core voltage, and bus/core
speed. Mixed processor steppings is supported. However, the stepping of one processor cannot
be greater than one stepping back of the other.
be greater than one stepping back of the other.
Processors must be installed in order. CPU 1 is located near the edge of the server board and
must be populated to operate the board.
Only Fully Buffered DIMMs (FBD) are supported on this server board.
Mixing memory type, size, speed, rank and/or memory vendors is not validated and is not
supported on this server board.
Non-ECC memory is not validated and is not supported in a server environment
For a list of supported memory for this server board, see the Intel
®
Compute Module MFS5000SI
Tested Memory List
in the Intel
®
Server Configurator Tool.
For a list of Intel supported operating systems, add-in cards, and peripherals for this server
board, see the Intel
®
Compute Module MFS5000SI Tested Hardware and Operating System List.
Only Dual-Core processors 5100 sequence or Quad-Core Intel
®
Xeon
®
processors 5300 or 5400
sequence, with system bus speeds of 1066/1333 MHz are supported on this server board.
Previous generation Intel
Previous generation Intel
®
Xeon
®
processors are not supported.
For best performance, the number of DIMMs installed should be balanced across both memory
branches. For example, a four-DIMM configuration will perform better than a two-DIMM
configuration and should be installed in DIMM Slots A1, B1, C1, and D1. An eight-DIMM
configuration will perform better than a six-DIMM configuration.
configuration and should be installed in DIMM Slots A1, B1, C1, and D1. An eight-DIMM
configuration will perform better than a six-DIMM configuration.
Normal Integrated BMC functionality (for example, KVM, monitoring, and remote media) is
disabled with the force BMC update jumper set to the “enabled” position (pins 1-2). The server
should never be run with the BMC force update jumper set in this position and should only be
used when the standard firmware update process fails. This jumper should remain in the default
(disabled) position (pins 2-3) when the compute module is running normally.
should never be run with the BMC force update jumper set in this position and should only be
used when the standard firmware update process fails. This jumper should remain in the default
(disabled) position (pins 2-3) when the compute module is running normally.
When performing the BIOS update procedure, the BIOS select jumper must be set to its default
position (pins 2-3).
Revision 1.4
Intel order number: E15154-007
30