Texas Instruments LM3423 Evaluation Board LM3423BBLSCSEV/NOPB LM3423BBLSCSEV/NOPB Datenbogen
Produktcode
LM3423BBLSCSEV/NOPB
SNVS574E – JULY 2008 – REVISED MAY 2013
Electrical Characteristics
(continued)
Specifications in standard type face are for T
J
= 25°C and those with boldface type apply over the full Operating
Temperature Range ( T
J
=
−
40°C to +150°C for LM3421Q0/LM3423Q0, T
J
=
−
40°C to +125°C for all others). Specifications
that differ between the two operating ranges will be identified in the Temp Range column as Q0 for T
J
=
−
40°C to +150°C
and as Q1 for T
J
=
−
40°C to +125°C. If no temperature range is indicated then the specification holds for both Q1 and Q0.
Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at T
likely parametric norm at T
J
= +25°C, and are provided for reference purposes only. Unless otherwise stated the following
condition applies: V
IN
= +14V.
Temp
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
Range
PULL-DOWN N-CHANNEL MosFETS
R
RPD
RPD Pull-down Resistance
Q1
300
145
Q0
350
R
FLT
FLT Pull-down Resistance
Q1
300
145
Ω
Q0
350
R
LRDY
LRDY Pull-down Resistance
Q1
300
135
Q0
350
THERMAL SHUTDOWN
T
SD
Thermal Shutdown Threshold
(4)
Q1
165
Q0
210
°C
T
HYS
Thermal Shutdown Hysteresis
(4)
25
THERMAL RESISTANCE
θ
JA
Junction to Ambient
(5)
16L TSSOP
37.4
°C/W
20L TSSOP
34.0
θ
JC
Junction to Exposed Pad (EP)
16L TSSOP
2.3
°C/W
20L TSSOP
2.3
(5)
Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for an reference
layout wherein the 16L TSSOP package has its EP pad populated with 9 vias and the 20L TSSOP has its EP pad populated with 12
vias. In applications where high maximum power dissipation exists, namely driving a large MosFET at high switching frequency from a
high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power dissipation applications,
the maximum ambient temperature may have to be derated. Maximum ambient temperature (T
layout wherein the 16L TSSOP package has its EP pad populated with 9 vias and the 20L TSSOP has its EP pad populated with 12
vias. In applications where high maximum power dissipation exists, namely driving a large MosFET at high switching frequency from a
high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power dissipation applications,
the maximum ambient temperature may have to be derated. Maximum ambient temperature (T
A-MAX
) is dependent on the maximum
operating junction temperature (T
J-MAX-OP
= 125°C for Q1, or 150°C for Q0), the maximum power dissipation of the device in the
application (P
D-MAX
), and the junction-to ambient thermal resistance of the package in the application (
θ
JA
), as given by the following
equation: T
A-MAX
= T
J-MAX-OP
– (
θ
JA
× P
D-MAX
). In most applications there is little need for the full power dissipation capability of this
advanced package. Under these circumstances, no vias would be required and the thermal resistances would be 104 °C/W for the 16L
TSSOP and 86.7 °C/W for the 20L TSSOP. It is possible to conservatively interpolate between the full via count thermal resistance and
the no via count thermal resistance with a straight line to get a thermal resistance for any number of vias in between these two limits.
TSSOP and 86.7 °C/W for the 20L TSSOP. It is possible to conservatively interpolate between the full via count thermal resistance and
the no via count thermal resistance with a straight line to get a thermal resistance for any number of vias in between these two limits.
Copyright © 2008–2013, Texas Instruments Incorporated
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