Texas Instruments LM3423 Evaluation Board LM3423BBLSCSEV/NOPB LM3423BBLSCSEV/NOPB Datenbogen
Produktcode
LM3423BBLSCSEV/NOPB
SNVS574E – JULY 2008 – REVISED MAY 2013
Electrical Characteristics
(continued)
Specifications in standard type face are for T
J
= 25°C and those with boldface type apply over the full Operating
Temperature Range ( T
J
=
−
40°C to +150°C for LM3421Q0/LM3423Q0, T
J
=
−
40°C to +125°C for all others). Specifications
that differ between the two operating ranges will be identified in the Temp Range column as Q0 for T
J
=
−
40°C to +150°C
and as Q1 for T
J
=
−
40°C to +125°C. If no temperature range is indicated then the specification holds for both Q1 and Q0.
Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at T
likely parametric norm at T
J
= +25°C, and are provided for reference purposes only. Unless otherwise stated the following
condition applies: V
IN
= +14V.
Temp
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
Range
ERROR AMPLIFIER
V
REF
CSH Reference Voltage
With Respect to AGND
1.210
1.235
1.260
V
Error Amplifier Input Bias
-0.6
0
0.6
Current
µA
COMP Sink / Source Current
Q1
35
22
30
Q0
36
Transconductance
100
µA/V
Linear Input Range
(4)
±125
mV
Transconductance Bandwidth
-6dB Unloaded Response
(4)
0.5
1.0
MHz
OFF TIMER
Minimum Off-time
RCT = 1V through
Q1
75
35
ns
1 k
Ω
Q0
90
R
RCT
RCT Reset Pull-down
Q1
120
36
Ω
Resistance
Q0
125
V
RCT
V
IN
/25 Reference Voltage
V
IN
= 14V
Q1
585
540
565
mV
Q0
590
f
Continuous Conduction
2.2 nF > C
T
> 470 pF
25/(C
T
R
T
)
Hz
Switching Frequency
PWM COMPARATOR
COMP to PWM Offset
700
800
900
mV
CURRENT LIMIT (IS)
I
LIM
Current Limit Threshold
215
245
275
mV
I
LIM
Delay to Output
Q1
75
35
Q0
90
ns
Leading Edge Blanking Time
115
210
325
HIGH SIDE TRANSCONDUCTANCE AMPLIFIER
Input Bias Current
11.5
µA
Transconductance
20
119
mA/V
Input Offset Current
-1.5
0
1.5
µA
Input Offset Voltage
-7
0
7
mV
Transconductance Bandwidth
I
CSH
= 100 µA
250
500
kHz
(4)
GATE DRIVER (GATE)
R
SRC(GATE)
GATE Sourcing Resistance
GATE = High
2.0
6.0
Ω
R
SNK(GATE)
GATE Sinking Resistance
GATE = Low
1.3
4.5
DIM DRIVER (DIM, DDRV)
nDIM
VTH
nDIM / UVLO Threshold
1.185
1.240
1.285
V
nDIM
HYS
nDIM Hysteresis Current
Q1
25
20
23
µA
Q0
26
R
SRC(DDRV)
DDRV Sourcing Resistance
DDRV = High
13.5
30.0
Ω
R
SNK(DDRV)
DDRV Sinking Resistance
DDRV = Low
3.5
10.0
(4)
These electrical parameters are specified by design, and are not verified by test.
6
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