Texas Instruments IC MCU 16B MSP430G2202IN20 PDIP-20 TID MSP430G2202IN20 Datenbogen
Produktcode
MSP430G2202IN20
MSP430G2x32
MSP430G2x02
MSP430G2x02
SLAS723H – DECEMBER 2010 – REVISED MAY 2013
Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
Bit can be read and written.
rw-0,1:
Bit can be read and written. It is reset or set by PUC.
rw-(0,1):
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
7
6
5
4
3
2
1
0
00h
ACCVIE
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
WDTIE
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
interval timer mode.
OFIE
Oscillator fault interrupt enable
NMIIE
(Non)maskable interrupt enable
ACCVIE
Flash access violation interrupt enable
Address
7
6
5
4
3
2
1
0
01h
Table 7. Interrupt Flag Register 1 and 2
Address
7
6
5
4
3
2
1
0
02h
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on V
Reset on V
CC
power-on or a reset condition at the RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault.
PORIFG
Power-On Reset interrupt flag. Set on V
CC
power-up.
RSTIFG
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V
CC
power-up.
NMIIFG
Set via RST/NMI pin
Address
7
6
5
4
3
2
1
0
03h
10
Copyright © 2010–2013, Texas Instruments Incorporated