Texas Instruments BQ27505EVM - BQ27505 System-Side, Single-Cell Impedance Track??? Technology Evaluation Module BQ27505E BQ27505EVM Datenbogen
Produktcode
BQ27505EVM
Not Recommended for New Designs
www.ti.com
SLUS884 – FEBRUARY 2009
4.4
ACCESS MODES
The bq27505 provides three security modes (FULL ACCESS, UNSEALED, and SEALED) that control
data flash access permissions, according to
data flash access permissions, according to
. Data Flash refers to those data flash locations,
specified in
, that are accessible to the user. Manufacture Information refers to the three 32-byte
blocks.
Table 4-6. Data Flash Access
Security Mode
Data Flash
Manufacture Information
FULL ACCESS
R/W
R/W
UNSEALED
R/W
R/W
SEALED
None
R(A); R/W(B)
Although FULL ACCESS and UNSEALED modes appear identical, only FULL ACCESS allows the
bq27505 to write access-mode transition keys.
bq27505 to write access-mode transition keys.
4.5
SEALING/UNSEALING DATA FLASH
The bq27505 implements a key-access scheme to transition between SEALED, UNSEALED, and
FULL-ACCESS modes. Each transition requires that a unique set of two keys be sent to the bq27505 via
the Control( ) control command. The keys must be sent consecutively, with no other data being written to
the Control( ) register in between. Note that to avoid conflict, the keys must be different from the codes
presented in the CNTL DATA column of
FULL-ACCESS modes. Each transition requires that a unique set of two keys be sent to the bq27505 via
the Control( ) control command. The keys must be sent consecutively, with no other data being written to
the Control( ) register in between. Note that to avoid conflict, the keys must be different from the codes
presented in the CNTL DATA column of
subcommands.
When in SEALED mode, the CONTROL_STATUS [SS] bit is set, but when the UNSEAL keys are
correctly received by the bq27505, the [SS] bit is cleared. When the full-access keys are correctly
received, then the CONTROL_STATUS [FAS] bit is cleared.
correctly received by the bq27505, the [SS] bit is cleared. When the full-access keys are correctly
received, then the CONTROL_STATUS [FAS] bit is cleared.
Both the sets of keys for each level are 2 bytes each in length and are stored in data flash. The UNSEAL
key (stored at Unseal Key 0 and Unseal Key 1) and the FULL-ACCESS key (stored at Full-Access Key
0 and Full-Access Key 1) can only be updated when in FULL-ACCESS mode. The order of the keys is
Key 1 followed by Key 0. The order of the bytes entered through the Control( ) command is the reverse of
what is read from the part. For example, if the Key 1 and Key 0 of the Unseal Keys returns 0x1234 and
0x5678, then the Control( ) should supply 0x3412 and 0x7856 to unseal the part.
key (stored at Unseal Key 0 and Unseal Key 1) and the FULL-ACCESS key (stored at Full-Access Key
0 and Full-Access Key 1) can only be updated when in FULL-ACCESS mode. The order of the keys is
Key 1 followed by Key 0. The order of the bytes entered through the Control( ) command is the reverse of
what is read from the part. For example, if the Key 1 and Key 0 of the Unseal Keys returns 0x1234 and
0x5678, then the Control( ) should supply 0x3412 and 0x7856 to unseal the part.
4.6
DATA FLASH SUMMARY
summarizes the data flash locations available to the user, including their default, minimum, and
maximum values.
Table 4-7. Data Flash Summary
Subclass
Data
Min
Max
Default
Class
Subclass
Offset
Name
Units
ID
Type
Value
Value
Value
Configuration
2
Safety
0
OT Chg
I2
0
1200
550
0.1°C
Configuration
2
Safety
2
OT Chg Time
U1
0
60
2
s
Configuration
2
Safety
3
OT Chg Recovery
I2
0
1200
500
0.1°C
Configuration
2
Safety
5
OT Dsg
I2
0
1200
600
0.1°C
Configuration
2
Safety
7
OT Dsg Time
U1
0
60
2
s
Configuration
2
Safety
8
OT Dsg Recovery
I2
0
1200
550
0.1°C
Charge Inhibit
Configuration
32
0
Charge Inhibit Temp Low
I2
–400
1200
0
0.1°C
Temp Low
Charge Inhibit
Configuration
32
2
Charge Inhibit Temp High
I2
–400
1200
450
0.1°C
Temp High
Temp
Configuration
32
4
Temp Hys
I2
0
100
50
0.1°C
Hysteresis
Configuration
34
Charge
2
Charging Voltage
I2
0
4600
4200
mV
Configuration
34
Charge
4
Delta Temp
I2
0
500
50
0.1°C
Copyright © 2009, Texas Instruments Incorporated
GENERAL DESCRIPTION
21
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