Texas Instruments TPS51100EVM-001 Evaluation Module TPS51100EVM-001 TPS51100EVM-001 Datenbogen
Produktcode
TPS51100EVM-001
www.ti.com
4
Test Set-Up
V1
V4
−
+
FAN
+
−
S5
S3
JP1
V2
−
+
V3
−
+
−
+
A3
J5
J1
J3
J8
J7
JP6
JP2
JP4
V
V5IN
V
VTT OUT
0 V to 5 V
V
VDDQ IN
1.3 V to 3.4 V
LOAD2
1.25 V/ 0.9 V
3 A
4.75 V
to
5.25 V
LOAD1
1.25 V/ 0.9 V
< 10 mA
4.1
5-V DC Source (V
V5IN
)
4.2
Core Voltage Source (V
VDDQ IN
)
4.3
Termination Voltage Source (V
VTT OUT
)
Test Set-Up
Figure 3
shows the basic test set up recommended to evaluate the TPS51100EVM. Please note that
although all grounds are common, their connections should remain separate as noted in.
Figure 3. TPS51100EVM Recommended Test Set-Up
V
V5IN
should be a DC voltage source capable of delivering 5 V at 500 mA with a power handling capability
of at least 2.5 W. V
V5IN
should be connected between pins V5IN and V5IN_GND. V
V5IN
supplies the
TPS51100 operating current and powers the S3 and S5 sleep state switches.
V
VDDQ IN
is a DC voltage source capable of delivering 1.5 VDC to 3.4 VDC at 3.5 ADC with a power
handling capability of at least 12 W. V
VDDQ IN
should be connected to between pins VDDQ IN and V5IN
GND. V
VDDQ IN
supplies the source current for VLDOIN and the VDDQSNS reference voltage for the
TPS51100.
V
VTT OUT
source is used to test the sink capability of the VTT pin. V
TT OUT
must be able to source 3 A of
current at 5 V. A blocking diode should be placed in series with V
VTT OUT
to limit the sink current and
prevent reverse current into V
VTT OUT
. V
VTT OUT
should be connected between pins VTT OUT and GND
OUT. V
VTT OUT
and LOAD2 should never be on at the same time.
SLUU201–JULY 2004
5
Using the TPS51100