Texas Instruments THS7303EVM Evaluation Module THS7303EVM THS7303EVM Datenbogen

Produktcode

THS7303EVM

A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read

DATA

Slave Address

From Transmitter

From Receiver

ACK

Acknowledge

(From Receiver)

I C Device Address and

Read/Write Bit

R/W

ACK

Stop

Condition

Acknowledge

(Receiver)

Last Data Byte

SDA

First Data

Byte

Start

Condition

Acknowledge

(Transmitter)

ACK

Other

Data Bytes

A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read

DATA

Slave Address

Transmitter

Receiver

ACK

Acknowledge

(From

Receiver)

I C Device Address and

Read/Write Bit

R/W

ACK

Stop

Condition

Acknowledge

(From

Transmitter)

Last Data Byte

SDA

ACK

First Data

Byte

Start

Condition

Not

Acknowledge

(Transmitter)

Other

Data Bytes

THS7303

SLOS479B

–

OCTOBER 2005

–

REVISED MARCH 2011

www.ti.com

During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop condition. This sequence terminates a read cycle, as shown in

Figure 77

and

Figure 78

. Note

that the THS7303 does not allow multiple read transfers to occur. See the

Example: Reading from the THS7303

section for the proper procedure on reading from the THS7303.

Figure 75. I

C Write Cycle

Figure 76. Multiple Byte Write Transfer

Figure 77. I

C Read Cycle