Texas Instruments TLV320AIC3105 Evaluation Module (EVM) and USB motherboard TLV320AIC3105EVM-K TLV320AIC3105EVM-K Datenbogen
Produktcode
TLV320AIC3105EVM-K
RIGHT-JUSTIFIED MODE
BCLK
WCLK
1
0
0
1
0
T0149-01
1/fs
LSB
MSB
Left Channel
Right Channel
2
2
SDIN/SDOUT
n–1
n–1
n–2
n–2
n–3
n–3
LEFT-JUSTIFIED MODE
SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008
.........................................................................................................................................
www.ti.com
The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in Master
mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In
continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated,
so in general the number of bit clocks per frame is two times the data width. For example, if data width is chosen
as 16 bits, then 32 bit clocks are generated per frame. If the bit clock signal in master mode is to be used by a
PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be used. These cases
result in a low jitter bit clock signal being generated, having frequencies of 32 × f
mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In
continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated,
so in general the number of bit clocks per frame is two times the data width. For example, if data width is chosen
as 16 bits, then 32 bit clocks are generated per frame. If the bit clock signal in master mode is to be used by a
PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be used. These cases
result in a low jitter bit clock signal being generated, having frequencies of 32 × f
S
or 64 × f
S
. In the cases of
20-bit and 24-bt data width in master mode, the bit clocks generated in each frame are not all of equal period,
due to the device not having a clean 40 × f
due to the device not having a clean 40 × f
S
or 48 × f
S
clock signal readily available. The average frequency of
the bit clock signal is still accurate in these cases (being 40 × f
S
or 48 × f
S
), but the resulting clock signal has
higher jitter than in the 16-bit and 32-bit cases.
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC3105 further includes programmability to place the DOUT line in the high-impedance state during
all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit
clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in
multiple codecs able to use a single audio serial data bus.
The TLV320AIC3105 further includes programmability to place the DOUT line in the high-impedance state during
all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit
clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in
multiple codecs able to use a single audio serial data bus.
When the audio serial data bus is powered down while configured in master mode, the pins associated with the
interface are put into a high-impedance state.
interface are put into a high-impedance state.
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
Figure 17. Right-Justified Serial Data Bus Mode Operation
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
24
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s):