Texas Instruments TLV320AIC3105 Evaluation Module (EVM) and USB motherboard TLV320AIC3105EVM-K TLV320AIC3105EVM-K Datenbogen
Produktcode
TLV320AIC3105EVM-K
BCLK
WCLK
0
0
T0152-01
1/fs
LSB
LSB
LSB MSB
MSB
Left Channel
Right Channel
1
1
2
2
SDIN/SDOUT
n–1
n–1
n–1
n–2
n–3
n–3
n–4
n–2
TDM DATA TRANSFER
SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008
.........................................................................................................................................
www.ti.com
Figure 20. DSP Serial Data Bus Mode Operation
Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock
bit-clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By
changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the
serial data output driver (DOUT) can also be programmed to the high-impedance state during all bit clocks
except when valid data is being put onto the bus. This allows other codecs to be programmed with different
offsets and to drive their data onto the same DOUT line, just in a different slot. For incoming data, the codec
simply ignores data on the bus except where it is expected based on the programmed offset.
bit-clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By
changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the
serial data output driver (DOUT) can also be programmed to the high-impedance state during all bit clocks
except when valid data is being put onto the bus. This allows other codecs to be programmed with different
offsets and to drive their data onto the same DOUT line, just in a different slot. For incoming data, the codec
simply ignores data on the bus except where it is expected based on the programmed offset.
Note that the location of the data when an offset is programmed is different, depending on what transfer mode is
selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in
the frame. This differs from left-justified mode, where the left- and right-channel data are always a half-frame
apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left- and
right-channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in
selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in
the frame. This differs from left-justified mode, where the left- and right-channel data are always a half-frame
apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left- and
right-channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in
for the two cases.
26
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