Texas Instruments THS7364 Evaluation Module THS7364EVM THS7364EVM Datenbogen
Produktcode
THS7364EVM
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SD1 OUT
SD2 OUT
SD3 OUT
Disable SD
GND
Disable FHD
FHD1 OUT
FHD2 OUT
FHD3 OUT
Bypass FHD
SD1 IN
SD2 IN
SD3 IN
NC
(1)
V
S+
NC
FHD1 IN
FHD2 IN
FHD3 IN
Bypass SD
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SBOS530 – AUGUST 2010
PIN CONFIGURATION
PW PACKAGE
TSSOP-20
(TOP VIEW)
(1) NC = No connection.
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
SD1 IN
1
I
Standard-definition video input, channel 1; LPF = 9.5 MHz
SD2 IN
2
I
Standard-definition video input, channel 2; LPF = 9.5 MHz
SD3 IN
3
I
Standard-definition video input, channel 3; LPF = 9.5 MHz
NC
4
—
No internal connection
V
S+
5
I
Positive power-supply pin; connect to +2.7 V up to +5 V
NC
6
—
No internal connection
FHD1 IN
7
I
Full high-definition video input, channel 1; LPF = 72 MHz
FHD2 IN
8
I
Full high-definition video input, channel 2; LPF = 72 MHz
FHD3 IN
9
I
Full high-definition video input, channel 3; LPF = 72 MHz
Bypass all SD channel filters. Logic high bypasses the internal filters and logic low engages the
Bypass SD
10
I
internal filters.
Bypass all FHD channel filters. Logic high bypasses the internal filters and logic low engages the
Bypass FHD
11
I
internal filters.
FHD3 OUT
12
O
Full high-definition video output, channel 3; LPF = 72 MHz
FHD2 OUT
13
O
Full high-definition video output, channel 2; LPF = 72 MHz
FHD1 OUT
14
O
Full high-definition video output, channel 1; LPF = 72 MHz
Disable full high-definition channels. Logic high disables the FHD channels and logic low enables
Disable FHD
15
I
the FHD channels.
GND
16
I
Ground pin for all internal circuitry
Disable standard definition channels. Logic high disables the SD channels and logic low enables the
Disable SD
17
I
SD channels.
SD3 OUT
18
O
Standard-definition video output, channel 3; LPF = 9.5 MHz
SD2 OUT
19
O
Standard-definition video output, channel 2; LPF = 9.5 MHz
SD1 OUT
20
O
Standard-definition video output, channel 1; LPF = 9.5 MHz
Copyright © 2010, Texas Instruments Incorporated
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