Texas Instruments TPS65810 Evaluation Module TPS65810EVM TPS65810EVM Datenbogen

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TPS65810EVM
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INTERRUPT CONTROLLER – I
2
C REGISTERS
SLVS658B – MARCH 2006 – REVISED FEBRUARY 2007
SYSTEM STATUS MONITORED BY INTERRUPT CONTROLLER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER ADC_READING_HI, B7: CONVERSION COMPLETE;
INTERNAL STATUS BITS (NO I
2
C REGISTER BIT AVAILABLE: INPUT OUT OF RANGE (HI OR LO), ANLG1 PIN IMPEDANCE TO AGND2 EXCEEDS 1 m
Ω.
See additional details in the
section.
OTHER SYSTEM STATUS: THERMAL FAULT DETECTED
The I
2
C registers that control an interrupt generation (INT: HI
→LO) are shown below. The HEX address for each
register is shown by the register name, together with the R or W functionality for the register bits. Shaded values
indicate default initial power-up values.
INTERRUPT AND POWER GOOD FAULT MANAGEMENT REGISTERS
B7
B6
B5
B4
B3
B2
B1
B0
INTMASK1, ADDRESS=03, ALL BITS R/W
Bit name
MASK_ISM1
MASK_ISM2
MASK_ISM3
MASK_ILDO1
MASK_ILDO2
MASK_ILDO3
MASK_ILDO4
MASK_ILDO5
Function
MASK INT by
MASK INT by
MASK INT by
MASK INT by
MASK INT by
Mask INT by
MASK INT by
MASK INT by
SM1 PGOOD
SM2 PGOOD
SM3 PGOOD
LDO1 PGOOD
LDO2 PGOOD
LDO3 PGOOD
LDO4 PGOOD
LDO5 PGOOD
FAULT
FAULT
FAULT
FAULT
FAULT
FAULT
FAULT
FAULT
When 0
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
When 1
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
INTMASK2, ADDRESS=04, ALL BITS R/W
Bit name
MASK_IADC
MASK_IANLG1
MASK_IGPIO2
MASK_IGPIO1
MASK_ITHSHU
MASK_ICHGS
MASK_IADC_H
MASK_IADC_L
T
T
I
O
Function
MASKS INT BY
MASKS INT BY
MASKS INT BY
MASKS INT BY
MASKS INT BY
MASK INT BY
MASK INT BY
MASK INT BY
ADC END OF
ANLG1 HIGH
GPIO2 EDGE
GPIO1 EDGE
THERMAL
CHG_STAT
ADC INPUT
ADC INPUT
CONVERSION
IMPEDANCE
TRANSITION
TRANSITION
FAULT
REGISTER
ABOVE HI
BELOW LO
BITS
LIMIT
LIMIT
When 0
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
When 1
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
INT_ACK1, ADDRESS=05, ALL BITS R/W
Bit name
ACK_SM1
ACK_SM2
ACK_SM3
ACK_LDO1
ACK_LDO2
ACK_LDO3
ACK_LDO4
ACK_LDO5
Function
SM1 INT
SM2 INT
SM3 INT
LDO1 INT
LDO2 INT
LDO3 INT
LDO4 INT
LDO5 INT
REQUEST
REQUEST
REQUEST
REQUEST
REQUEST
REQUEST
REQUEST
REQUEST
When 0
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
When 1
SM1 PGOOD
SM2 PGOOD
SM3 OVP
LDO1 PGOOD
LDO2 PGOOD
LDO3 PGOOD
LDO4 PGOOD
LDO5 PGOOD
FAULT
FAULT
FAULT
FAULT
FAULT
FAULT
FAULT
FAULT
GENERATED
GENERATED
GENERATED
GENERATED
GENERATED
GENERATED
GENERATED
GENERATED
INT
INT
INT
INT
INT
INT
INT
INT
INT_ACK2, ADDRESS=06, ALL BITS READ ONLY
Bit name
ACK_ADC
ACK_ANLG1
ACK_GPIO2
ACK_GPIO1
ACK_THSHUT
ACK_CHGSTA
ACK_ADC_HI
ACK_ADC_LO
T
Function
ADC INT
ANLG1
GPIO2 INT
GPIO1 INT
THERMAL
CHARGER INT
ADC INT
ADC INT
REQUEST 1
COMPARATO
REQUEST
REQUEST
FAULT INT
REQUEST
REQUEST 2
REQUEST 3
R INT
REQUEST
REQUEST
When 0
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
CLEAR FLAG
When 1
ADC DONE
ANLG1 HIGH
GPIO2 EDGE
GPIO1 EDGE
THERMAL
CHARGER
ADC INPUT
ADC INPUT
GENERATED
IMPEDANCE
GENERATED
GENERATED
FAULT
STATUS
ABOVE HI
BELOW LO
INT REQUEST
DETECTION
INT REQUEST
INT REQUEST
GENERATED
CHANGE
LIMIT
LIMIT
GENERATED
INT REQUEST
GENERATED
GENERATED
GENERATED
INT REQUEST
INT REQUEST
INT REQUEST
INT REQUEST
PGOODFAULT_MASK, ADDRESS=07, ALL BITS R/W
Bit name
PGOOD SM1
PGOOD SM2
PGOOD SM3
PGOOD LDO1
PGOOD LDO2
PGOOD LDO3
PGOOD LDO4
PGOOD LDO5
Function
MASK PGOOD
MASK PGOOD
MASK PGOOD
MASK PGOOD
MASK PGOOD
MASK PGOOD
MASK PGOOD
MASK PGOOD
FAULT BY
FAULT BY
FAULT BY
FAULT BY
FAULT BY
FAULT BY
FAULT BY
FAULT BY
SM1
SM2
SM3
LDO1
LDO2
LDO3
LDO4
LDO5
When 0
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
When 1
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
40
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