Texas Instruments 2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference TPS51206EVM-745 TPS51206EVM-745 Datenbogen
Produktcode
TPS51206EVM-745
3
TPS51206EVM-745 Recommended Test Setup
.......................................................................
4
DDR2(0.9VTT) Load Regulation
........................................................................................
5
DDR3 (0.75VTT) Load Regulation
......................................................................................
6
DDR3L (0.675VTT) Load Regulation
..................................................................................
7
DDR4 (0.6VTT) Load Regulation
........................................................................................
8
DDR2 (0.9VTTREF) Load Regulation
.................................................................................
9
DDR3 (0.75VTTREF) Load Regulation
.................................................................................
10
DDR3L (0.675VTTREF) Load Regulation
.............................................................................
11
DDR4 (0.6VTTREF) Load Regulation
..................................................................................
12
DDR2 (0.9VTT) Dropout Voltage
.......................................................................................
13
DDR3 (0.75VTT) Dropout Voltage
.....................................................................................
14
DDR3L (0.675VTT) Dropout Voltage
..................................................................................
15
DDR4 (0.6VTT) Dropout Voltage
.......................................................................................
16
DDR2 (0.9VTT) 1.8-A Sink/Source
.....................................................................................
17
DDR3 (0.75VTT) 1.5-A Sink/Source
...................................................................................
18
DDR3L (0.75VTT) 1.35-A Sink/Source
................................................................................
19
DDR4 (0.6VTT) 1.2-A Sink/Source
......................................................................................
20
DDR3 (0.75VTT) S5 Enable Turnon
...................................................................................
21
DDR3 (0.75VTT) S5 Enable Turnoff
...................................................................................
22
DDR3 (0.75VTT) S3 Enable Turnon
...................................................................................
23
DDR3 (0.75VTT) S3 Enable Turnoff
...................................................................................
24
DDR3 Bode plot
...........................................................................................................
25
TPS51206EVM-745 Top Layer Assembly Drawing
...................................................................
26
TPS51206EVM-745 Top Layer
..........................................................................................
27
TPS51206EVM-745 Internal Layer 1
..................................................................................
28
TPS51206EVM-745 Internal Layer 2
...................................................................................
29
TPS51206EVM-745 Bottom Layer
......................................................................................
30
TPS51206EVM-745 Bottom Layer Assembly
..........................................................................
List of Tables
1
TPS51206EVM-745 Electrical Performance Specifications
...........................................................
2
Transient Load Selection
..................................................................................................
3
Source Transient Load Selection
.........................................................................................
4
Sink Transient Load Selection
............................................................................................
5
S3, S5 Enable Selection
...................................................................................................
6
Functions of Each Test Point
............................................................................................
7
Bill of Materials
............................................................................................................
2
Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination
SLUU515
–
August 2011
Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and
Copyright
©
2011, Texas Instruments Incorporated
DDR4