Texas Instruments Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices FLINK3V8BT-85/NOPB FLINK3V8BT-85/NOPB Datenbogen
Produktcode
FLINK3V8BT-85/NOPB
FPD-Link Evaluation Kit User’s Manual
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 3 of 25
Date: 9/25/2007
Page 3 of 25
Introduction:
National Semiconductor - Interface Products Group FPD-Link evaluation kit contains
a Transmitter (Tx) board, a Receiver (Rx) board along with interfacing cables. This
kit will demonstrate the DS90C385A/DS90CF386 chipsets interfacing from test
equipment or a graphics controller using Low Voltage Differential Signaling (LVDS)
to a receiver board.
The Transmitter board accepts LVTTL/LVCMOS RGB signals from the graphics
controller along with the clock signal. The LVDS Transmitter converts the
LVTTL/LVCMOS parallel lines into four serialized LVDS data pairs plus a LVDS
clock. The serial data streams toggle at 3.5 times the clock rate.
The Receiver board accepts the LVDS serialized data streams plus clock and
converts the data back into parallel LVTTL/LVCMOS RGB signals and clock for the
panel timing controller.
The user needs to provide the proper RGB inputs and clock to the Transmitter and
also provide a proper interface from the Receiver output to the panel timing
controller or test equipment. A cable conversion board or harness scramble may be
necessary depending on type of cable/connector interface used. A power down
feature is also provided that reduces current draw when the link is not required.
a Transmitter (Tx) board, a Receiver (Rx) board along with interfacing cables. This
kit will demonstrate the DS90C385A/DS90CF386 chipsets interfacing from test
equipment or a graphics controller using Low Voltage Differential Signaling (LVDS)
to a receiver board.
The Transmitter board accepts LVTTL/LVCMOS RGB signals from the graphics
controller along with the clock signal. The LVDS Transmitter converts the
LVTTL/LVCMOS parallel lines into four serialized LVDS data pairs plus a LVDS
clock. The serial data streams toggle at 3.5 times the clock rate.
The Receiver board accepts the LVDS serialized data streams plus clock and
converts the data back into parallel LVTTL/LVCMOS RGB signals and clock for the
panel timing controller.
The user needs to provide the proper RGB inputs and clock to the Transmitter and
also provide a proper interface from the Receiver output to the panel timing
controller or test equipment. A cable conversion board or harness scramble may be
necessary depending on type of cable/connector interface used. A power down
feature is also provided that reduces current draw when the link is not required.