Texas Instruments Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices FLINK3V8BT-85/NOPB FLINK3V8BT-85/NOPB Datenbogen
Produktcode
FLINK3V8BT-85/NOPB
FPD-Link Evaluation Kit User’s Manual
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 5 of 25
Date: 9/25/2007
Page 5 of 25
Chipsets support up to 18-bit or 24-bit AM-TFT LCD Panels for any VGA (640X480),
SVGA (800X600), XGA (1024X768), and Single/Dual Pixel SXGA (1280X1024)
resolutions.
Because of the non-periodic nature of STN-DD SHFCLK, the Chipset may not work
with all D-STN panels. The PLL CLK input of the Transmitter requires a free running
periodic SHFCLK. Most Graphics Controller can provide a separate pin with a free
running clock. In this case the STN-DD SHFCLK can be sent as Data while the free
running clock can be used as SHFCLK for the PLL ref CLK. For example, C&T's
65550's WEC (Pin 102) can be programmed to provide a free running clock using
the BMP (Bios Modification Program). Please refer to STN Application using (AN-
1056) for more information on STN support.
Refer to the proper datasheet information on Chipsets (Tx/Rx) provided on each
board for more detailed information.
SVGA (800X600), XGA (1024X768), and Single/Dual Pixel SXGA (1280X1024)
resolutions.
Because of the non-periodic nature of STN-DD SHFCLK, the Chipset may not work
with all D-STN panels. The PLL CLK input of the Transmitter requires a free running
periodic SHFCLK. Most Graphics Controller can provide a separate pin with a free
running clock. In this case the STN-DD SHFCLK can be sent as Data while the free
running clock can be used as SHFCLK for the PLL ref CLK. For example, C&T's
65550's WEC (Pin 102) can be programmed to provide a free running clock using
the BMP (Bios Modification Program). Please refer to STN Application using (AN-
1056) for more information on STN support.
Refer to the proper datasheet information on Chipsets (Tx/Rx) provided on each
board for more detailed information.