Texas Instruments Evaluation Module for TLV70433 TLV70433DBVEVM-712 TLV70433DBVEVM-712 Datenbogen
Produktcode
TLV70433DBVEVM-712
500 mV/div
100 mV/div
V
OUT
I
IL
C
1
C
2
T = T + P
J
A
D
JA
q
?
Thermal Guidelines and Layout Recommendations
www.ti.com
5.2
Output Load Transient
illustrates the output voltage transient response to a load step transient of 10 mA to 150 mA.
Oscilloscope channel C
1
shows the current step and channel C
2
shows the V
OUT
voltage response
Note:
•
C
1
: Load step of 10 mA to 150 mA;
•
C
2
, V
OUT
: Output voltage transient response.
Figure 2. Step Load and Transient Response
6
Thermal Guidelines and Layout Recommendations
Thermal management is a key design component of any power converter, and is especially important
when the power dissipation in the LDO is high. Use
when the power dissipation in the LDO is high. Use
to approximate the maximum power
dissipation for a given ambient temperature.
Where:
T
J
= junction temperature
T
A
= ambient temperature
P
D
= power dissipation in the IC (in watts)
q
JA
= thermal resistance from junction to ambient
(1)
All temperatures are in degrees Celsius (°C).
The maximum silicon junction temperature, T
J
, must not be allowed to exceed +125°C. The layout design
must use copper trace and plane areas effectively as thermal sinks, in order not to allow T
J
to exceed the
absolute maximum ratings under all temperature conditions and voltage conditions across the application.
Designers should carefully consider the thermal design of the PCB for optimal performance over
temperature. For this EVM,
temperature. For this EVM,
illustrates one way in which the V
IN
plane, connected to pin 2 of both
the SOT89 and SOT23 package, can be used to thermally cool the LDO by sinking dissipated power. The
PCB is a two-layer board with 2-oz. copper on top and bottom layers.
PCB is a two-layer board with 2-oz. copper on top and bottom layers.
4
TLV70433DBVEVM-712, TLV70433PKEVM-712 Evaluation Modules
SBVU017 – January 2011
© 2011, Texas Instruments Incorporated