Texas Instruments EVM430-F6736 - MSP430F6736 EVM for Metering EVM430-F6736 EVM430-F6736 Datenbogen
Produktcode
EVM430-F6736
MSP430F673x
MSP430F672x
MSP430F672x
SLAS731C – DECEMBER 2011 – REVISED FEBRUARY 2013
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
1.8 V/
f
TA
Timer_A input clock frequency
External: TACLK
25
MHz
3.0 V
Duty cycle = 50% ± 10%
All capture inputs.
1.8 V/
t
TA,cap
Timer_A capture timing
20
ns
Minimum pulse width required for
3.0 V
capture.
eUSCI (UART Mode) - Recommended Operating Conditions
PARAMETER
CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
f
eUSCI
eUSCI input clock frequency
External: UCLK
f
SYSTEM
MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
f
BITCLK
5
MHz
(equals baud rate in MBaud)
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
UCGLITx = 0
10
15
25
UCGLITx = 1
30
50
85
2.0 V/3.0
t
t
UART receive deglitch time
(1)
ns
V
UCGLITx = 2
50
80
150
UCGLITx = 3
70
120
200
(1)
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
correctly recognized their width should exceed the maximum specification of the deglitch time.
eUSCI (SPI Master Mode) - Recommended Operating Conditions
PARAMETER
CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
f
eUSCI
eUSCI input clock frequency
f
SYSTEM
MHz
Duty cycle = 50% ± 10%
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
UCSTEM = 0, UCMODEx = 01 or 10
2.0 V/3.0 V
150
STE lead time, STE
t
STE,LEAD
ns
active to clock
UCSTEM = 1, UCMODEx = 01 or 10
2.0 V/3.0 V
150
UCSTEM = 0, UCMODEx = 01 or 10
2.0 V/3.0 V
200
STE lag time, Last clock
t
STE,LAG
ns
to STE inactive
UCSTEM = 1, UCMODEx = 01 or 10
2.0 V/3.0 V
200
2.0 V
50
UCSTEM = 0, UCMODEx = 01 or 10
3.0 V
30
STE access time, STE
t
STE,ACC
ns
active to SIMO data out
2.0 V
50
UCSTEM = 1, UCMODEx = 01 or 10
3.0 V
30
2.0 V
40
UCSTEM = 0, UCMODEx = 01 or 10
STE disable time, STE
3.0 V
25
t
STE,DIS
inactive to SIMO high
ns
2.0 V
40
impedance
UCSTEM = 1, UCMODEx = 01 or 10
3.0 V
25
2.0 V
50
SOMI input data setup
t
SU,MI
ns
time
3.0 V
30
(1)
f
UCxCLK
= 1/2t
LO/HI
with tL
O/HI
= max(t
VALID,MO(eUSCI)
+ t
SU,SI(Slave)
, t
SU,MI(eUSCI)
+ t
VALID,SO(Slave)
).
For the slave's parameters t
SU,SI(Slave)
and t
VALID,SO(Slave)
refer to the SPI parameters of the attached slave.
64
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